vestigia

Detect where execution depends on secrets.
git clone git://git.ppad.tech/vestigia.git
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qemu-crypto.patch (2648B)


      1 QEMU's Arm CPU models all have the cryptographic extension (AES,
      2 PMULL, SHA1, SHA2, SHA3, SHA512, SM3, SM4), and none can be told to
      3 lack it, while CPUs built without it (a Raspberry Pi 4's Cortex-A72)
      4 run in the field: a program choosing its code by the CPU's features
      5 runs other code on them than any emulated CPU leads it to. crypto=off,
      6 on any AArch64 model, clears the extension's ID register fields, as
      7 such a CPU reports them: the instructions UNDEF, and a guest's HWCAP
      8 and ID register reads say they are absent.
      9 
     10 --- a/target/arm/cpu.c
     11 +++ b/target/arm/cpu.c
     12 @@ -1581,6 +1581,41 @@
     13      ARMCPU *cpu = ARM_CPU(obj);
     14  
     15      return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
     16 +}
     17 +
     18 +static bool aarch64_cpu_get_crypto(Object *obj, Error **errp)
     19 +{
     20 +    ARMCPU *cpu = ARM_CPU(obj);
     21 +
     22 +    return cpu_isar_feature(aa64_aes, cpu);
     23 +}
     24 +
     25 +/*
     26 + * crypto=off removes the cryptographic extension (AES, PMULL, SHA1,
     27 + * SHA2, SHA3, SHA512, SM3, SM4), as a CPU built without it reports,
     28 + * from the ID registers: the instructions UNDEF, and a guest's
     29 + * HWCAP and ID register reads say they are absent.
     30 + */
     31 +static void aarch64_cpu_set_crypto(Object *obj, bool value, Error **errp)
     32 +{
     33 +    ARMCPU *cpu = ARM_CPU(obj);
     34 +
     35 +    if (value) {
     36 +        if (!cpu_isar_feature(aa64_aes, cpu)) {
     37 +            error_setg(errp, "'crypto' feature cannot be enabled on "
     38 +                       "this CPU");
     39 +        }
     40 +        return;
     41 +    }
     42 +    FIELD_DP64_IDREG(&cpu->isar, ID_AA64ISAR0, AES, 0);
     43 +    FIELD_DP64_IDREG(&cpu->isar, ID_AA64ISAR0, SHA1, 0);
     44 +    FIELD_DP64_IDREG(&cpu->isar, ID_AA64ISAR0, SHA2, 0);
     45 +    FIELD_DP64_IDREG(&cpu->isar, ID_AA64ISAR0, SHA3, 0);
     46 +    FIELD_DP64_IDREG(&cpu->isar, ID_AA64ISAR0, SM3, 0);
     47 +    FIELD_DP64_IDREG(&cpu->isar, ID_AA64ISAR0, SM4, 0);
     48 +    FIELD_DP32_IDREG(&cpu->isar, ID_ISAR5, AES, 0);
     49 +    FIELD_DP32_IDREG(&cpu->isar, ID_ISAR5, SHA1, 0);
     50 +    FIELD_DP32_IDREG(&cpu->isar, ID_ISAR5, SHA2, 0);
     51  }
     52  
     53  static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
     54 @@ -1738,6 +1773,11 @@
     55          object_property_set_description(obj, "aarch64",
     56                                          "Set on/off to enable/disable aarch64 "
     57                                          "execution state ");
     58 +        object_property_add_bool(obj, "crypto", aarch64_cpu_get_crypto,
     59 +                                 aarch64_cpu_set_crypto);
     60 +        object_property_set_description(obj, "crypto",
     61 +                                        "Set off to remove the "
     62 +                                        "cryptographic extension");
     63      }
     64  #ifndef CONFIG_USER_ONLY
     65      if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||