commit 628e38440d5b27024c7bfaa7720117f8be29d69d
parent 80b530d9bc9977e9f8e14174ef86a9fefbe64bf0
Author: Jared Tobin <jared@jtobin.io>
Date: Tue, 27 Oct 2026 11:19:14 +0400
merge impl/contract: data-independent-timing contracts
record --contract arm-dit or intel-doitm has the plugin fingerprint
the operands of every instruction outside the ISA's contract in the
objects --object names, as it does a division's. The tables are
generated from the vendors' statements: Arm's A64 ISA XML (2022-12),
every encoding with its source registers, and Intel's list 768547
(2026-02-23). diff reports such an instruction run on other operands
under outside, apart from the origins: the contract says nothing of
its time either way, so it qualifies a report rather than failing
it. A division stays an operand origin. The report (vestigia/diff-v4)
names the ISA and the contract and counts what ran outside it; runs
recorded under other contracts are refused. The probe divides its
secret in floating point and checks each ISA's contract finds it.
Diffstat:
14 files changed, 3665 insertions(+), 83 deletions(-)
diff --git a/CHANGELOG b/CHANGELOG
@@ -1,5 +1,22 @@
# Changelog
+- 0.2.0 (unreleased)
+ * Data-independent-timing contracts: `record --contract arm-dit`
+ or `intel-doitm`, with `--object` and `--objdump`, has the plugin
+ fingerprint the operands of every instruction outside the ISA's
+ contract in the objects named, as it does a division's. The
+ tables are transcribed from the vendors' statements: Arm's A64
+ ISA XML (2022-12), every encoding with its source registers, and
+ Intel's list 768547 (2026-02-23).
+ * `diff` reports such an instruction on other operands under
+ `outside`, apart from the origins, with its text, and how many
+ ran (vestigia/diff-v4, which also names the ISA and contract, and
+ gives an operand origin its text where the watch list named it).
+ Runs recorded under other contracts are refused.
+ * `record` appends the guest's ISA to its dump.
+ * `diffOf` takes a `contract`; the command finds LLVM's
+ `llvm-objdump` through `$VESTIGIA_OBJDUMP`.
+
- 0.1.0 (2026-10-22)
* Initial version, with two instruments over a harness that marks
its secret (`vestigia.h`, defined by `vestigia.c`, which serves
diff --git a/README.md b/README.md
@@ -108,19 +108,46 @@ loaded an object at different addresses. A guest reading
`/dev/urandom` still reads the host's.
`record` appends to its dump how the run was made: the program and
-its arguments, the size of the guest's environment, and the exit
-status, which the report gives for each run. `diff` refuses a run of
-another program, or with arguments of another number or length, or an
-environment of another size, than the first run's, each of which lays
-the guest's stack out apart; and a control that does not repeat the
-first run's arguments.
+its arguments, the size of the guest's environment, the exit status,
+and the guest's ISA, which the report gives for each run. `diff`
+refuses a run of another program, or with arguments of another
+number or length, or an environment of another size, than the first
+run's, each of which lays the guest's stack out apart; and a control
+that does not repeat the first run's arguments.
+
+### Under a contract: `record --contract`
+
+An ISA's data-independent-timing contract lists the instructions
+whose time does not depend on their data: Arm's `PSTATE.DIT`
+(`arm-dit`) and Intel's DOITM (`intel-doitm`), transcribed from the
+vendors' own statements (`lib/Vestigia/Contract/Arm.hs`, generated
+from Arm's A64 ISA XML, and `lib/Vestigia/Contract/Intel.hs`, from
+Intel's list, each citing its release). Under one, `record`
+disassembles the objects the program loads whose path contains an
+`--object` text (with LLVM's `llvm-objdump`: `--objdump`, else
+`$VESTIGIA_OBJDUMP`), and the plugin fingerprints the operands of
+every instruction outside the contract, as it does a division's:
+
+```
+$ vestigia record --contract intel-doitm --object /bin/probe \
+> --dump run-1 -- ./probe 00000005
+```
+
+One run equally often on other operands in some run is reported by
+`diff` apart from the origins, under `outside`, with its text: the
+contract says nothing of its time either way, so it qualifies a
+clean report rather than failing it. The report names the contract
+and the ISA, and how many instructions outside the contract ran.
+Runs compared must have been recorded under the same contract. A
+division is an operand origin, as without a contract.
### As derivations
The flake's `lib.<system>` holds `traceOf` and `diffOf`, which run
either instrument as a derivation over a list of runs; an
`x86_64-linux` run executes on any builder for that system, and its
-report is cached. `diffOf` repeats the first run as its control.
+report is cached. `diffOf` repeats the first run as its control, and takes a
+`contract` to record under.
`nix/lib.nix` holds the same for a consumer's own nixpkgs, beside
`version`.
@@ -134,7 +161,7 @@ vestigia.lib.x86_64-linux.diffOf {
```
The output holds `trace.json` (`vestigia/trace-v2`) or `diff.json`
-(`vestigia/diff-v3`), the runs kept or the plugin's dumps, what the
+(`vestigia/diff-v4`), the runs kept or the plugin's dumps, what the
harness printed, and the wall time.
## Two instruments
@@ -165,9 +192,14 @@ ppad-poly1305, and ppad-secp256k1.
* An address origin can be an address that an earlier secret branch
moved, a heap block or stack frame laid out apart, rather than one
computed from the secret.
-* Divisions alone are read for their operands. Floating-point
- division and square root, and multiplication on cores that time it
- by its operands, are left to a timing instrument.
+* Without a contract, divisions alone are read for their operands.
+ Under one, an instruction's source registers are read off its
+ encoding (AArch64) or its operands (x86_64, with the registers some
+ instructions read without naming); flags are not read, and a
+ 256- or 512-bit vector is read by its low 128 bits, all of it QEMU
+ names. A contract covers the ISA's statement, not a core's: a core
+ that does not honour it (or a deployment that does not enable it)
+ is for a timing instrument.
* A GHC harness wants `-with-rtsopts=-xr1G -V0`, against the
runtime's terabyte reservation and its interval timer. GHC calls
and returns by jumping, so its origins have no callers, and a
diff --git a/app/Main.hs b/app/Main.hs
@@ -15,6 +15,7 @@ module Main (
import Control.Exception (IOException, try)
import Control.Monad (unless, when)
+import qualified Data.List as L
import qualified Data.ByteString as BS
import Data.Char (toUpper)
import qualified Data.Map.Strict as M
@@ -28,22 +29,26 @@ import qualified Data.Text.Encoding as TE
import qualified Data.Text.Encoding.Error as TEE
import qualified Data.Text.IO as TIO
import System.Directory
- (createDirectoryIfMissing, doesDirectoryExist, doesFileExist,
- getTemporaryDirectory, removeFile)
+ (canonicalizePath, createDirectoryIfMissing, doesDirectoryExist,
+ doesFileExist, getTemporaryDirectory, removeFile)
import System.Environment (getArgs, getEnvironment, lookupEnv)
import System.Exit (ExitCode(..), exitWith)
import System.FilePath (takeFileName, (</>))
import Text.Read (readMaybe)
import System.IO
(IOMode(..), hClose, hPutStrLn, openTempFile, stderr, withBinaryFile)
-import System.Process (proc, waitForProcess, withCreateProcess)
+import System.Process
+ (proc, readCreateProcessWithExitCode, waitForProcess, withCreateProcess)
import qualified System.Process as P
import Paths_vestigia (version)
+import Vestigia.Contract
+ (Contract(..), Line, contractIsa, contractName, readContract,
+ readDisassembly, watchSection)
import Vestigia.Diff
(Dump(..), Kind(..), Named(..), Run(..), diffDesigned, divergenceJson,
- divergenceSummary, dvCallers, dvOrigins, inObject, inOffset, inPc,
- layoutApart, readDump, restrictTo, runApart)
+ divergenceSummary, dvCallers, dvOrigins, dvOutside, inObject, inOffset,
+ inPc, layoutApart, readDump, restrictTo, runApart)
import Vestigia.Json (encode)
import Vestigia.Layout (fixLayout)
import Vestigia.Memcheck (Memcheck, readMemcheck)
@@ -62,6 +67,8 @@ data Opts = Opts {
, oObjects :: ![T.Text]
, oControls :: ![FilePath]
, oDesigned :: ![FilePath]
+ , oContract :: !(Maybe T.Text)
+ , oObjdump :: !(Maybe FilePath)
}
main :: IO ()
@@ -96,6 +103,7 @@ usage e = do
\[--object TEXT]... -- PROGRAM [ARG...]"
, " vestigia read [--out FILE] [--object TEXT]... RUN..."
, " vestigia record [--qemu PATH] [--plugin PATH] --dump FILE \
+ \[--contract NAME [--objdump PATH] [--object TEXT]...] \
\-- PROGRAM [ARG...]"
, " vestigia diff [--out FILE] [--addr2line PATH] \
\[--object TEXT]... [--control DUMP]... [--designed DUMP]... \
@@ -112,8 +120,15 @@ usage e = do
, "record executes PROGRAM under QEMU with vestigia's plugin and"
, "dumps its leakage trace per instruction, with how it was run;"
, "diff compares dumps of runs that differ only in a secret and"
- , "reports where they diverge (vestigia/diff-v3), naming sources"
+ , "reports where they diverge (vestigia/diff-v4), naming sources"
, "with addr2line."
+ , "--contract (arm-dit or intel-doitm, the program's ISA's) has"
+ , "record also fingerprint the operands of every instruction"
+ , "outside that data-independent-timing contract, in the objects"
+ , "the program loads whose path contains an --object TEXT (all,"
+ , "with none), read with objdump (--objdump, else"
+ , "$VESTIGIA_OBJDUMP, else llvm-objdump); diff reports those whose"
+ , "operands differed beside the origins."
, "--object keeps origins in objects whose path contains TEXT;"
, "--control names a run repeating the first run's secret, and"
, "what differs in it is unsteady, not an origin."
@@ -127,7 +142,7 @@ usage e = do
-- options before the program; "--" ends them
options :: [String] -> Either String (Opts, [String])
options = go (Opts Nothing Nothing Nothing Nothing Nothing Nothing
- Nothing [] [] [])
+ Nothing [] [] [] Nothing Nothing)
where
go o xs = case xs of
("--" : rest) -> Right (o, rest)
@@ -144,6 +159,8 @@ options = go (Opts Nothing Nothing Nothing Nothing Nothing Nothing
go o { oControls = oControls o <> [ p ] } rest
("--designed" : p : rest) ->
go o { oDesigned = oDesigned o <> [ p ] } rest
+ ("--contract" : c : rest) -> go o { oContract = Just (T.pack c) } rest
+ ("--objdump" : p : rest) -> go o { oObjdump = Just p } rest
(x : _) | take 2 x == "--" -> Left ("unknown option: " <> x)
_ -> Right (o, xs)
@@ -303,6 +320,16 @@ record o prog progArgs = do
qemu <- tool (oQemu o) ("VESTIGIA_QEMU_" <> fmap toUpper isa)
("qemu-" <> isa)
plugin <- tool (oPlugin o) "VESTIGIA_PLUGIN" "libvestigia-qemu.so"
+ -- under a contract, the instructions outside it in the objects
+ -- under audit, for the plugin to watch
+ contract <- traverse (\name -> case readContract name of
+ Just c | contractIsa c == isa -> pure c
+ | otherwise -> refuseRecord (T.unpack name <> " speaks to "
+ <> contractIsa c <> ", and " <> prog <> " is " <> isa)
+ Nothing -> refuseRecord ("no contract named " <> T.unpack name
+ <> "; arm-dit and intel-doitm are known"))
+ (oContract o)
+ watch <- traverse (\c -> watchList o qemu c prog progArgs) contract
-- QEMU maps the guest's libraries and heap in its own address
-- space, wherever its own allocations leave room, and those vary
-- with how its threads run: a second malloc arena, or a large block
@@ -322,10 +349,13 @@ record o prog progArgs = do
r <- try (withCreateProcess
((proc qemu (guest
<> [ "-seed", "0"
- , "-plugin", plugin <> ",out=" <> dump, prog ]
+ , "-plugin", plugin <> ",out=" <> dump
+ <> maybe "" (",watch=" <>) watch
+ , prog ]
<> progArgs))
{ P.env = Just ((tunables, host) : others) })
(\_ _ _ ph -> waitForProcess ph))
+ for_ watch removeFile
case r of
Left e -> do
hPutStrLn stderr ("vestigia: cannot run " <> qemu <> ": "
@@ -336,9 +366,80 @@ record o prog progArgs = do
-- in the secret alone from runs laid out apart: the guest's
-- environment is QEMU's, with its own tunables restored
appendRun dump (prog : progArgs)
- (others <> [ (tunables, v) | Just v <- [ own ] ]) c
+ (others <> [ (tunables, v) | Just v <- [ own ] ]) c isa contract
exitWith c
+refuseRecord :: String -> IO a
+refuseRecord e = do
+ hPutStrLn stderr ("vestigia: " <> e)
+ exitWith (ExitFailure 2)
+
+-- the plugin's watch list under a contract, written to a temporary
+-- file: every instruction outside it in the objects the program loads
+-- (and the program's own) whose path contains an --object text, all
+-- of them with none
+watchList :: Opts -> FilePath -> Contract -> FilePath -> [String]
+ -> IO FilePath
+watchList o qemu c prog progArgs = do
+ objdump <- tool (oObjdump o) "VESTIGIA_OBJDUMP" "llvm-objdump"
+ loaded <- loadedObjects qemu prog progArgs
+ objects <- fmap L.nub (traverse canonicalizePath (prog : loaded))
+ let kept = [ p | p <- objects
+ , null (oObjects o)
+ || any (`T.isInfixOf` T.pack p) (oObjects o) ]
+ sections <- traverse (\p -> do
+ ls <- disassemble objdump c p
+ pure (watchSection c p ls))
+ kept
+ tmp <- getTemporaryDirectory
+ (path, h) <- openTempFile tmp "vestigia.watch"
+ hClose h
+ TIO.writeFile path (T.concat sections)
+ pure path
+
+-- the shared objects a program loads, as its dynamic loader resolves
+-- them, run under QEMU so that any ISA's are found
+loadedObjects :: FilePath -> FilePath -> [String] -> IO [FilePath]
+loadedObjects qemu prog progArgs = do
+ r <- try (readCreateProcessWithExitCode
+ (proc qemu ([ "-E", "LD_TRACE_LOADED_OBJECTS=1", prog ]
+ <> progArgs)) "")
+ case r of
+ Left e -> refuseRecord ("cannot run " <> qemu <> ": "
+ <> show (e :: IOException))
+ Right (ExitSuccess, out, _) -> pure (concatMap object (lines out))
+ Right (ExitFailure n, _, err) -> refuseRecord ("the loader could not \
+ \list what " <> prog <> " loads (exit " <> show n <> "): " <> err)
+ where
+ -- "\tNAME => PATH (0x...)" or "\tPATH (0x...)"
+ object l = case words l of
+ (_ : "=>" : p@('/' : _) : _) -> [ p ]
+ (p@('/' : _) : _) -> [ p ]
+ _ -> []
+
+-- an object's instructions, its executable sections disassembled
+-- whole: GHC's LLVM backend gives its code the type of data, which a
+-- disassembly by symbol would print as bytes
+disassemble :: FilePath -> Contract -> FilePath -> IO [Line]
+disassemble objdump c obj = do
+ headers <- objdumped [ "--section-headers", obj ]
+ let sections = [ name | l <- lines headers
+ , (_ : name : _ : _ : kinds) <- [ words l ]
+ , "TEXT" `elem` kinds ]
+ out <- objdumped ([ "-D" ] <> fmap ("--section=" <>) sections
+ <> [ "-M" | c == IntelDoitm ] <> [ "intel" | c == IntelDoitm ]
+ <> [ obj ])
+ pure (readDisassembly (T.pack out))
+ where
+ objdumped args = do
+ r <- try (readCreateProcessWithExitCode (proc objdump args) "")
+ case r of
+ Right (ExitSuccess, out, _) -> pure out
+ Right (ExitFailure n, _, err) -> refuseRecord (objdump <> " "
+ <> unwords args <> " failed (exit " <> show n <> "): " <> err)
+ Left e -> refuseRecord ("cannot run " <> objdump <> ": "
+ <> show (e :: IOException))
+
-- the architecture an ELF program is built for, as QEMU names its
-- user-mode emulators: the header's machine, at byte 18
machineOf :: FilePath -> IO String
@@ -358,10 +459,11 @@ machineOf prog = do
-- append a run's record to its dump (Vestigia.Diff.readDump): its
-- arguments' bytes, its environment's variables and the bytes they
--- take, and its exit status
+-- take, its exit status, the guest's ISA, and any contract it was
+-- recorded under
appendRun :: FilePath -> [String] -> [(String, String)] -> ExitCode
- -> IO ()
-appendRun dump args env code = do
+ -> String -> Maybe Contract -> IO ()
+appendRun dump args env code isa contract = do
enc <- getFileSystemEncoding
let bytes s = GF.withCStringLen enc s BS.packCStringLen
as <- traverse bytes args
@@ -371,7 +473,9 @@ appendRun dump args env code = do
| a <- as ]
<> [ "N " <> showHex (length es) "" <> " "
<> showHex (sum (fmap ((+ 1) . BS.length) es)) ""
- , "X " <> show (exitStatus code) ]
+ , "X " <> show (exitStatus code)
+ , "M " <> isa ]
+ <> [ "G " <> T.unpack (contractName c) | Just c <- [ contract ] ]
where
byte w = case showHex w "" of
[ d ] -> [ '0', d ]
@@ -405,6 +509,15 @@ diff o paths = do
refuse (p <> " is a control, but does not repeat the \
\arguments of " <> p0 <> ", the run it controls")
[] -> pure ()
+ -- runs recorded under other contracts watched other instructions
+ case zip (paths <> oDesigned o <> oControls o)
+ (dumps <> designed <> controls) of
+ ((p0, first) : rest) -> for_ rest $ \(p, d) ->
+ when (dpContract d /= dpContract first || dpIsa d /= dpIsa first) $
+ refuse (p <> " was recorded for another ISA or under another \
+ \contract than " <> p0 <> "; runs compared must watch the \
+ \same instructions")
+ [] -> pure ()
-- runs laid out apart differ wherever they touch memory, not by
-- the secret: such runs are refused, not compared
case zip paths dumps of
@@ -424,11 +537,11 @@ diff o paths = do
[] -> pure ()
let dv = restrictTo (oObjects o)
(diffDesigned controls dumps designed)
+ let sites = fmap snd (dvOrigins dv) <> dvOutside dv
places <- symbolize addr2line $
- [ (obj, inOffset i) | (_, i) <- dvOrigins dv
- , Just obj <- [ inObject i ] ]
+ [ (obj, inOffset i) | i <- sites, Just obj <- [ inObject i ] ]
-- the calls that reached each origin
- <> [ (obj, a) | (_, i) <- dvOrigins dv
+ <> [ (obj, a) | i <- sites
, Just (stacks, _) <- [ M.lookup (inPc i) (dvCallers dv) ]
, calls <- stacks, (Just obj, a) <- calls ]
let doc = encode (divergenceJson (T.pack (showVersion version))
diff --git a/etc/probe/harness.c b/etc/probe/harness.c
@@ -8,8 +8,10 @@
* Its secret, the first argument in hex (of one width for every
* secret, so that runs lay out alike), reaches a loop's bound, a
* table index, which of two calls a helper returns to, a dividend,
- * a divisor, and, on a path the third secret alone takes, another
- * table index; a constant-time select reaches none of them.
+ * a divisor, a floating-point division (outside either ISA's
+ * data-independent-timing contract), and, on a path the third secret
+ * alone takes, another table index; a constant-time select reaches
+ * none of them.
*/
#include <stdio.h>
#include <stdlib.h>
@@ -72,6 +74,12 @@ __attribute__((noinline)) unsigned divide_memory(unsigned s) {
#endif
}
+/* a secret divided in floating point, which neither Arm's DIT nor
+ Intel's DOITM covers */
+__attribute__((noinline)) unsigned fpdivide(unsigned s) {
+ return (unsigned)((double)s / 7.0);
+}
+
/* a table index on a path one secret takes */
__attribute__((noinline)) unsigned rare(unsigned s) {
if ((s & 0xffu) == 0xc3u) return table[(s >> 1) & 0xffu];
@@ -85,7 +93,7 @@ __attribute__((noinline)) unsigned ct(unsigned s, unsigned p) {
int main(int argc, char **argv) {
unsigned s = (unsigned)strtoul(argc > 1 ? argv[1] : "0", NULL, 16);
- unsigned out[7];
+ unsigned out[8];
for (int i = 0; i < 256; i++) table[i] = (unsigned char)i;
vestigia_secret(&s, sizeof s);
out[0] = branchy(s);
@@ -95,8 +103,9 @@ int main(int argc, char **argv) {
out[4] = divide_memory(s);
out[5] = rare(s);
out[6] = ct(s, 1);
+ out[7] = fpdivide(s);
vestigia_public(out, sizeof out);
- printf("%u %u %u %u %u %u %u\n", out[0], out[1], out[2], out[3],
- out[4], out[5], out[6]);
+ printf("%u %u %u %u %u %u %u %u\n", out[0], out[1], out[2], out[3],
+ out[4], out[5], out[6], out[7]);
return 0;
}
diff --git a/lib/Vestigia/Contract.hs b/lib/Vestigia/Contract.hs
@@ -0,0 +1,395 @@
+{-# OPTIONS_HADDOCK prune #-}
+{-# LANGUAGE OverloadedStrings #-}
+
+-- |
+-- Module: Vestigia.Contract
+-- Copyright: (c) 2026 Jared Tobin
+-- License: MIT
+-- Maintainer: Jared Tobin <jared@ppad.tech>
+--
+-- An ISA's data-independent-timing contract, and what it makes of
+-- each instruction of an object: one it covers takes a time
+-- independent of its data; one it does not, run on operands that
+-- depend on the secret, is outside the contract; and a division is
+-- variable-time on either ISA. Control flow and system instructions
+-- are left to the comparison of what ran.
+--
+-- An object is read through LLVM's disassembler (@llvm-objdump@), in
+-- Intel syntax on x86_64. On AArch64 an instruction is matched by its
+-- encoding against Arm's own ('Vestigia.Contract.Arm'), its source
+-- registers read off the fields the encoding names. On x86_64 it is
+-- matched by its mnemonic and opcode byte against Intel's list
+-- ('Vestigia.Contract.Intel'), its source registers read off its
+-- operands: every register operand outside a memory reference, but
+-- the first where the instruction only writes it, and the registers
+-- some instructions read without naming.
+--
+-- What is outside the contract and reads data becomes the watch
+-- list the QEMU plugin is given: each such instruction, by its
+-- address in its object, with the registers to fingerprint before it
+-- runs, as the plugin fingerprints a division's operands.
+
+module Vestigia.Contract (
+ Contract(..)
+ , contractName
+ , contractSource
+ , contractIsa
+ , readContract
+ , Line(..)
+ , readDisassembly
+ , Register(..)
+ , Verdict(..)
+ , classify
+ , watchSection
+ ) where
+
+import Data.Bits (popCount, shiftR, testBit, (.&.))
+import Data.Char (isHexDigit)
+import qualified Data.List as L
+import qualified Data.Map.Strict as M
+import qualified Data.Set as S
+import qualified Data.Text as T
+import Data.Word (Word32, Word8)
+import Numeric (readHex, showHex)
+
+import qualified Vestigia.Contract.Arm as Arm
+import qualified Vestigia.Contract.Intel as Intel
+import Vestigia.Contract.Types
+
+-- | A data-independent-timing contract: Arm's @PSTATE.DIT@, or
+-- Intel's DOITM.
+data Contract =
+ ArmDit
+ | IntelDoitm
+ deriving (Eq, Show)
+
+contractName :: Contract -> T.Text
+contractName c = case c of
+ ArmDit -> "arm-dit"
+ IntelDoitm -> "intel-doitm"
+
+-- | The release of the vendor's own statement the table transcribes.
+contractSource :: Contract -> T.Text
+contractSource c = case c of
+ ArmDit -> "Arm A64 ISA XML, 2022-12"
+ IntelDoitm -> "Intel 768547, Table 1, 2026-02-23"
+
+-- | The ISA a contract speaks to, as QEMU names it.
+contractIsa :: Contract -> String
+contractIsa c = case c of
+ ArmDit -> "aarch64"
+ IntelDoitm -> "x86_64"
+
+readContract :: T.Text -> Maybe Contract
+readContract t = case t of
+ "arm-dit" -> Just ArmDit
+ "intel-doitm" -> Just IntelDoitm
+ _ -> Nothing
+
+-- | One instruction as the disassembler prints it: its address in
+-- the object, its raw form (an AArch64 word, or x86_64's bytes),
+-- any prefixes, its mnemonic, and its operands.
+data Line = Line {
+ lnAddress :: !Integer
+ , lnRaw :: ![Integer]
+ , lnPrefixes :: ![T.Text]
+ , lnMnemonic :: !T.Text
+ , lnOperands :: !T.Text
+ } deriving (Eq, Show)
+
+-- | The instructions of @llvm-objdump@'s disassembly; everything
+-- else it prints (headers, symbols, elided runs) is passed over.
+readDisassembly :: T.Text -> [Line]
+readDisassembly = concatMap line . T.lines
+ where
+ line l = case T.breakOn ":" (T.stripStart l) of
+ (a, rest)
+ | not (T.null a), T.all isHexDigit a
+ , Just body <- T.stripPrefix ":" rest
+ , [ (addr, "") ] <- readHex (T.unpack a)
+ , (raw, text) <- T.breakOn "\t" body
+ , Just ws <- traverse hexToken (T.words raw)
+ , not (null ws) ->
+ case filter (not . T.null)
+ (fmap T.strip (T.splitOn "\t" text)) of
+ [] -> []
+ fs -> let (ps, rest') = L.span (`S.member` prefixes) fs
+ in case rest' of
+ (m : ops) -> [ Line addr ws ps m
+ (uncomment (T.unwords ops)) ]
+ [] -> []
+ _ -> []
+ hexToken w
+ | T.all isHexDigit w, [ (v, "") ] <- readHex (T.unpack w) = Just v
+ | otherwise = Nothing
+ -- the disassembler's annotations, x86_64's after " # " and
+ -- AArch64's after " //": a target or a literal, never an operand
+ -- (an AArch64 immediate is "#" with no space after it)
+ uncomment t =
+ T.stripEnd (fst (T.breakOn " //" (fst (T.breakOn " # " t))))
+
+-- prefixes the disassembler prints as fields of their own
+prefixes :: S.Set T.Text
+prefixes = S.fromList
+ [ "lock", "rep", "repe", "repz", "repne", "repnz", "data16", "data32"
+ , "addr32", "notrack", "bnd", "xacquire", "xrelease", "cs", "ds"
+ , "es", "fs", "gs", "ss" ]
+
+-- | A register to fingerprint, as QEMU names it, by the bits read:
+-- from its low bit, so many of them.
+data Register = Register {
+ rgName :: !T.Text
+ , rgLow :: !Int
+ , rgWidth :: !Int
+ } deriving (Eq, Ord, Show)
+
+-- | What a contract makes of an instruction: covered by it; control
+-- flow or system, or reading no data; an integer division, which
+-- the plugin reads for itself; or outside the contract, with the
+-- registers it reads and whether it names memory.
+data Verdict =
+ Inside
+ | Excluded
+ | Division
+ | Watched ![Register] !Bool
+ deriving (Eq, Show)
+
+-- | Classify one instruction under a contract.
+classify :: Contract -> Line -> Verdict
+classify c l = case c of
+ ArmDit -> case lnRaw l of
+ [ w ] | w >= 0, w < 2 ^ (32 :: Int) -> arm (fromInteger w) l
+ _ -> Excluded
+ IntelDoitm -> intel l
+
+-- AArch64 ---------------------------------------------------------
+
+arm :: Word32 -> Line -> Verdict
+arm w l = case best of
+ Nothing -> Excluded
+ Just e
+ | any (`T.isPrefixOf` enName e) [ "UDIV_", "SDIV_" ] -> Division
+ | otherwise -> case enStatus e of
+ Covered -> Inside
+ Control -> Excluded
+ Outside ops -> case concatMap (register w) ops of
+ [] | not memory -> Excluded
+ rs -> Watched (L.nub rs) memory
+ where
+ memory = "[" `T.isInfixOf` lnOperands l
+ candidates = M.findWithDefault [] (bucket w) armIndex
+ best = case [ e | e <- candidates, w .&. enMask e == enValue e ] of
+ [] -> Nothing
+ es -> Just (L.maximumBy (\a b -> compare (fixed a) (fixed b)) es)
+ fixed e = popCount (enMask e)
+
+-- an encoding's group, bits 28 to 25
+bucket :: Word32 -> Word32
+bucket w = (w `shiftR` 25) .&. 0xf
+
+-- the encodings by every group their fixed bits allow
+armIndex :: M.Map Word32 [Encoding]
+armIndex = M.fromListWith (flip (<>))
+ [ (b, [ e ])
+ | e <- Arm.encodings
+ , b <- [ 0 .. 15 ]
+ , b .&. bucket (enMask e) == bucket (enValue e) ]
+
+register :: Word32 -> (Int, Operand) -> [Register]
+register w (lsb, op) =
+ let n = fromIntegral ((w `shiftR` lsb) .&. 31) :: Int
+ x = "x" <> T.pack (show n)
+ v = "v" <> T.pack (show n)
+ in case op of
+ OpX | n == 31 -> []
+ | otherwise -> [ Register x 0 64 ]
+ OpXSp | n == 31 -> [ Register "sp" 0 64 ]
+ | otherwise -> [ Register x 0 64 ]
+ OpW | n == 31 -> []
+ | otherwise -> [ Register x 0 32 ]
+ OpWSp | n == 31 -> [ Register "sp" 0 32 ]
+ | otherwise -> [ Register x 0 32 ]
+ OpQ -> [ Register v 0 128 ]
+ OpD -> [ Register v 0 64 ]
+ OpS -> [ Register v 0 32 ]
+ OpH -> [ Register v 0 16 ]
+ OpB -> [ Register v 0 8 ]
+ OpV -> [ Register v 0 (if testBit w 30 then 128 else 64) ]
+ OpVWhole -> [ Register v 0 128 ]
+
+-- x86_64 ----------------------------------------------------------
+
+intel :: Line -> Verdict
+intel l
+ | m `S.member` control || "J" `T.isPrefixOf` m = Excluded
+ | m == "DIV" || m == "IDIV" = Division
+ | Just op <- opcode (lnRaw l)
+ , (name, op) `S.member` intelRows = Inside
+ | null sources && not memory = Excluded
+ | otherwise = Watched (L.nub sources) memory
+ where
+ m = mnemonic l
+ -- a repeat prefix names a string instruction's row; on any other
+ -- it does nothing
+ name
+ | any (`elem` [ "rep", "repe", "repz", "repne", "repnz" ])
+ (lnPrefixes l)
+ , any (`T.isPrefixOf` m)
+ [ "MOVS", "STOS", "LODS", "CMPS", "SCAS", "INS", "OUTS" ] =
+ "REP_" <> m
+ | otherwise = m
+ operands = splitOperands (lnOperands l)
+ memory = any ("[" `T.isInfixOf`) operands
+ named = [ r | o <- operands, not ("[" `T.isInfixOf` o)
+ , Just r <- [ M.lookup (bare o) intelRegisters ] ]
+ explicit = case operands of
+ (o : _) | writesOnly m, not ("[" `T.isInfixOf` o) -> drop 1 named
+ _ -> named
+ sources = explicit <> M.findWithDefault [] m implicit
+
+intelRows :: S.Set (T.Text, Word8)
+intelRows = S.fromList Intel.instructions
+
+-- the mnemonic as Intel's list spells it: upper case, a condition by
+-- its list name, a 64-bit immediate move as a move
+mnemonic :: Line -> T.Text
+mnemonic l =
+ let m = T.toUpper (lnMnemonic l)
+ in case m of
+ "MOVABS" -> "MOV"
+ _ -> case [ p <> c' | p <- [ "CMOV", "SET" ]
+ , Just c <- [ T.stripPrefix p m ]
+ , Just c' <- [ M.lookup c conditions ] ] of
+ (n : _) -> n
+ [] -> m
+
+conditions :: M.Map T.Text T.Text
+conditions = M.fromList
+ [ ("O", "O"), ("NO", "NO"), ("B", "B"), ("C", "B"), ("NAE", "B")
+ , ("NB", "NB"), ("AE", "NB"), ("NC", "NB"), ("Z", "Z"), ("E", "Z")
+ , ("NZ", "NZ"), ("NE", "NZ"), ("BE", "BE"), ("NA", "BE")
+ , ("NBE", "NBE"), ("A", "NBE"), ("S", "S"), ("NS", "NS"), ("P", "P")
+ , ("PE", "P"), ("NP", "NP"), ("PO", "NP"), ("L", "L"), ("NGE", "L")
+ , ("NL", "NL"), ("GE", "NL"), ("LE", "LE"), ("NG", "LE")
+ , ("NLE", "NLE"), ("G", "NLE") ]
+
+-- control flow, system, and instructions that read no data
+control :: S.Set T.Text
+control = S.fromList
+ [ "CALL", "RET", "LOOP", "LOOPE", "LOOPNE", "SYSCALL", "SYSENTER"
+ , "INT", "INT3", "INTO", "UD1", "UD2", "HLT", "NOP", "PAUSE"
+ , "ENDBR32", "ENDBR64", "LFENCE", "MFENCE", "SFENCE", "CPUID"
+ , "RDTSC", "RDTSCP", "XGETBV", "RDRAND", "RDSEED", "ENTER", "LEAVE"
+ , "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHNTA"
+ , "PREFETCHW", "CLFLUSH", "CLFLUSHOPT" ]
+
+-- instructions that write their first operand without reading it
+writesOnly :: T.Text -> Bool
+writesOnly m =
+ ("V" `T.isPrefixOf` m && m /= "VZEROUPPER" && m /= "VZEROALL")
+ || "MOV" `T.isPrefixOf` m
+ || "CVT" `T.isPrefixOf` m
+ || any (`T.isPrefixOf` m) [ "SQRT", "RSQRT", "RCP" ]
+ || m `elem` [ "POPCNT", "LZCNT", "TZCNT", "PDEP", "PEXT", "BZHI"
+ , "BEXTR", "BLSI", "BLSR", "BLSMSK", "SARX", "LEA" ]
+
+-- registers read without being named
+implicit :: M.Map T.Text [Register]
+implicit = M.fromList
+ [ ("CBW", [ Register "rax" 0 8 ]), ("CWDE", [ Register "rax" 0 16 ])
+ , ("CDQE", [ Register "rax" 0 32 ]), ("CWD", [ Register "rax" 0 16 ])
+ , ("CDQ", [ Register "rax" 0 32 ]), ("CQO", [ Register "rax" 0 64 ])
+ , ("SAHF", [ Register "rax" 8 8 ])
+ , ("CMPXCHG", [ Register "rax" 0 64 ])
+ , ("CMPXCHG8B", fmap (\r -> Register r 0 32)
+ [ "rax", "rdx", "rbx", "rcx" ])
+ , ("CMPXCHG16B", fmap (\r -> Register r 0 64)
+ [ "rax", "rdx", "rbx", "rcx" ]) ]
+
+-- an operand less its masking and broadcast decorations
+bare :: T.Text -> T.Text
+bare = T.strip . T.takeWhile (/= '{')
+
+-- operands, split at the commas between them
+splitOperands :: T.Text -> [T.Text]
+splitOperands t
+ | T.null (T.strip t) = []
+ | otherwise = fmap T.strip (go 0 "" (T.unpack t))
+ where
+ go :: Int -> String -> String -> [T.Text]
+ go _ acc [] = [ T.pack (reverse acc) ]
+ go d acc (ch : rest) = case ch of
+ '[' -> go (d + 1) (ch : acc) rest
+ ']' -> go (d - 1) (ch : acc) rest
+ ',' | d == 0 -> T.pack (reverse acc) : go d "" rest
+ _ -> go d (ch : acc) rest
+
+-- the general and vector registers QEMU exposes, by their names in
+-- Intel syntax: a wide vector by its low 128 bits, which is all of
+-- it QEMU names
+intelRegisters :: M.Map T.Text Register
+intelRegisters = M.fromList $
+ concat
+ [ [ (r64, Register r64 0 64), (r32, Register r64 0 32)
+ , (r16, Register r64 0 16), (r8, Register r64 0 8) ]
+ | (r64, r32, r16, r8) <-
+ [ ("rax", "eax", "ax", "al"), ("rbx", "ebx", "bx", "bl")
+ , ("rcx", "ecx", "cx", "cl"), ("rdx", "edx", "dx", "dl")
+ , ("rsi", "esi", "si", "sil"), ("rdi", "edi", "di", "dil")
+ , ("rbp", "ebp", "bp", "bpl"), ("rsp", "esp", "sp", "spl") ]
+ <> [ (n, n <> "d", n <> "w", n <> "b")
+ | k <- [ 8 .. 15 :: Int ], let n = "r" <> T.pack (show k) ] ]
+ <> [ (h, Register r 8 8)
+ | (h, r) <- [ ("ah", "rax"), ("bh", "rbx"), ("ch", "rcx")
+ , ("dh", "rdx") ] ]
+ <> [ (p <> T.pack (show k), Register ("xmm" <> T.pack (show k)) 0 128)
+ | p <- [ "xmm", "ymm", "zmm" ], k <- [ 0 .. 15 :: Int ] ]
+
+-- the last opcode byte, past the prefixes, a REX, any VEX or EVEX
+-- payload, and the escape bytes
+opcode :: [Integer] -> Maybe Word8
+opcode bs = fmap fromInteger (go (dropWhile legacy bs))
+ where
+ legacy b = b `elem` [ 0x66, 0x67, 0xf0, 0xf2, 0xf3, 0x2e, 0x36
+ , 0x3e, 0x26, 0x64, 0x65 ]
+ go xs = case xs of
+ (b : rest) | b >= 0x40 && b <= 0x4f -> escaped rest
+ (0xd5 : _ : rest) -> at 0 rest
+ _ -> escaped xs
+ escaped xs = case xs of
+ (0xc5 : rest) -> at 1 rest
+ (0xc4 : rest) -> at 2 rest
+ (0x62 : rest) -> at 3 rest
+ (0x0f : 0x38 : rest) -> at 0 rest
+ (0x0f : 0x3a : rest) -> at 0 rest
+ (0x0f : rest) -> at 0 rest
+ _ -> at 0 xs
+ at k xs = case drop k xs of
+ (b : _) -> Just b
+ [] -> Nothing
+
+-- the watch list ----------------------------------------------------
+
+-- | The plugin's watch list for one object, at its path: an @O@ line
+-- naming it, then a @D@ line per division and a @U@ line per
+-- instruction outside the contract, each with its address and its
+-- text (a @U@ line with whether it names memory and the registers
+-- it reads, each as name:low:width, before the text).
+watchSection :: Contract -> FilePath -> [Line] -> T.Text
+watchSection c path ls = T.unlines $
+ ("O " <> T.pack path)
+ : concatMap entry ls
+ where
+ entry l = case classify c l of
+ Division -> [ "D " <> hex (lnAddress l) <> " " <> text l ]
+ Watched rs memory ->
+ [ T.unwords $
+ [ "U", hex (lnAddress l), if memory then "1" else "0"
+ , T.pack (show (length rs)) ]
+ <> [ rgName r <> ":" <> T.pack (show (rgLow r)) <> ":"
+ <> T.pack (show (rgWidth r)) | r <- rs ]
+ <> [ text l ] ]
+ _ -> []
+ text l = T.unwords (filter (not . T.null)
+ (lnPrefixes l <> [ lnMnemonic l, lnOperands l ]))
+ hex n = T.pack (showHex n "")
diff --git a/lib/Vestigia/Contract/Arm.hs b/lib/Vestigia/Contract/Arm.hs
@@ -0,0 +1,2184 @@
+{-# OPTIONS_HADDOCK prune #-}
+{-# LANGUAGE OverloadedStrings #-}
+
+-- |
+-- Module: Vestigia.Contract.Arm
+-- Copyright: (c) 2026 Jared Tobin
+-- License: MIT
+-- Maintainer: Jared Tobin <jared@ppad.tech>
+--
+-- Arm's data-independent-timing contract (@PSTATE.DIT@), encoding by
+-- encoding, generated from Arm's machine-readable specification.
+--
+-- == Source
+--
+-- /A64 ISA XML for A-profile Architecture/, version @2022-12@
+-- (package @ISA_A64_xml_A_profile-2022-12@, sha256
+-- @1839a9722eab26aa3bdcd91adeeaf2e6c5c6df085f0e096f949c55cbee7d1a5a@),
+-- retrieved 2026-10-27 from the Internet Archive mirror of Arm's
+-- exploration-tools release,
+-- @archive.org\/details\/arm-xml-a-profile-2022-12@, its md5
+-- matching the mirror's record.
+--
+-- == Rule
+--
+-- Every encoding of every A64 instruction section (type
+-- @instruction@, one per file) of the general, Advanced SIMD,
+-- floating-point, SIMD&FP load/store, and system classes; SVE and SME
+-- are left out. An instruction is covered exactly when its section's
+-- @\<operationalnotes\>@ name @PSTATE.DIT@, whose data-processing
+-- note reads:
+--
+-- > If PSTATE.DIT is 1: The execution time of this instruction is
+-- > independent of: The values of the data supplied in any of its
+-- > registers. The values of the NZCV flags.
+--
+-- An encoding's fixed bits are its class's register diagram with the
+-- encoding's own boxes over it. One not covered is control flow or
+-- system ('Control') where its pseudocode lies under
+-- @aarch64\/instrs\/branch\/@ or @aarch64\/instrs\/system\/@, or
+-- its section is of the system class; otherwise it is 'Outside', with
+-- its source registers: the five-bit register fields its assembler
+-- template names whose explanation is neither destination-only nor
+-- an address (a base register, or one holding an address).
+
+module Vestigia.Contract.Arm (
+ encodings
+ ) where
+
+import Vestigia.Contract.Types
+
+-- | Every encoding, in the specification's file order.
+encodings :: [Encoding]
+encodings =
+ [ Encoding "ABS_32_dp_1src" 0xfffffc00 0x5ac02000 Covered
+ , Encoding "ABS_64_dp_1src" 0xfffffc00 0xdac02000 Covered
+ , Encoding "ABS_asisdmisc_R" 0xff3ffc00 0x5e20b800 Covered
+ , Encoding "ABS_asimdmisc_R" 0xbf3ffc00 0x0e20b800 Covered
+ , Encoding "ADC_32_addsub_carry" 0xffe0fc00 0x1a000000 Covered
+ , Encoding "ADC_64_addsub_carry" 0xffe0fc00 0x9a000000 Covered
+ , Encoding "ADCS_32_addsub_carry" 0xffe0fc00 0x3a000000 Covered
+ , Encoding "ADCS_64_addsub_carry" 0xffe0fc00 0xba000000 Covered
+ , Encoding "ADD_32_addsub_ext" 0xffe00000 0x0b200000 Covered
+ , Encoding "ADD_64_addsub_ext" 0xffe00000 0x8b200000 Covered
+ , Encoding "ADD_32_addsub_imm" 0xff800000 0x11000000 Covered
+ , Encoding "ADD_64_addsub_imm" 0xff800000 0x91000000 Covered
+ , Encoding "ADD_32_addsub_shift" 0xff200000 0x0b000000 Covered
+ , Encoding "ADD_64_addsub_shift" 0xff200000 0x8b000000 Covered
+ , Encoding "ADD_asisdsame_only" 0xff20fc00 0x5e208400 Covered
+ , Encoding "ADD_asimdsame_only" 0xbf20fc00 0x0e208400 Covered
+ , Encoding "ADDG_64_addsub_immtags" 0xffc00000 0x91800000
+ (Outside [(5, OpXSp)])
+ , Encoding "ADDHN_asimddiff_N" 0xbf20fc00 0x0e204000 Covered
+ , Encoding "ADDP_asisdpair_only" 0xff3ffc00 0x5e31b800 Covered
+ , Encoding "ADDP_asimdsame_only" 0xbf20fc00 0x0e20bc00 Covered
+ , Encoding "ADDS_32S_addsub_ext" 0xffe00000 0x2b200000 Covered
+ , Encoding "ADDS_64S_addsub_ext" 0xffe00000 0xab200000 Covered
+ , Encoding "ADDS_32S_addsub_imm" 0xff800000 0x31000000 Covered
+ , Encoding "ADDS_64S_addsub_imm" 0xff800000 0xb1000000 Covered
+ , Encoding "ADDS_32_addsub_shift" 0xff200000 0x2b000000 Covered
+ , Encoding "ADDS_64_addsub_shift" 0xff200000 0xab000000 Covered
+ , Encoding "ADDV_asimdall_only" 0xbf3ffc00 0x0e31b800 Covered
+ , Encoding "ADR_only_pcreladdr" 0x9f000000 0x10000000 (Outside [])
+ , Encoding "ADRP_only_pcreladdr" 0x9f000000 0x90000000 (Outside [])
+ , Encoding "AESD_B_cryptoaes" 0xfffffc00 0x4e285800 Covered
+ , Encoding "AESE_B_cryptoaes" 0xfffffc00 0x4e284800 Covered
+ , Encoding "AESIMC_B_cryptoaes" 0xfffffc00 0x4e287800 Covered
+ , Encoding "AESMC_B_cryptoaes" 0xfffffc00 0x4e286800 Covered
+ , Encoding "AND_asimdsame_only" 0xbfe0fc00 0x0e201c00 Covered
+ , Encoding "AND_32_log_imm" 0xffc00000 0x12000000 Covered
+ , Encoding "AND_64_log_imm" 0xff800000 0x92000000 Covered
+ , Encoding "AND_32_log_shift" 0xff200000 0x0a000000 Covered
+ , Encoding "AND_64_log_shift" 0xff200000 0x8a000000 Covered
+ , Encoding "ANDS_32S_log_imm" 0xffc00000 0x72000000 Covered
+ , Encoding "ANDS_64S_log_imm" 0xff800000 0xf2000000 Covered
+ , Encoding "ANDS_32_log_shift" 0xff200000 0x6a000000 Covered
+ , Encoding "ANDS_64_log_shift" 0xff200000 0xea000000 Covered
+ , Encoding "ASRV_32_dp_2src" 0xffe0fc00 0x1ac02800 Covered
+ , Encoding "ASRV_64_dp_2src" 0xffe0fc00 0x9ac02800 Covered
+ , Encoding "AUTDA_64P_dp_1src" 0xfffffc00 0xdac11800 (Outside [(5, OpXSp)])
+ , Encoding "AUTDZA_64Z_dp_1src" 0xffffffe0 0xdac13be0 (Outside [])
+ , Encoding "AUTDB_64P_dp_1src" 0xfffffc00 0xdac11c00 (Outside [(5, OpXSp)])
+ , Encoding "AUTDZB_64Z_dp_1src" 0xffffffe0 0xdac13fe0 (Outside [])
+ , Encoding "AUTIA_64P_dp_1src" 0xfffffc00 0xdac11000 (Outside [(5, OpXSp)])
+ , Encoding "AUTIZA_64Z_dp_1src" 0xffffffe0 0xdac133e0 (Outside [])
+ , Encoding "AUTIA1716_HI_hints" 0xfffff23f 0xd503201f (Outside [])
+ , Encoding "AUTIASP_HI_hints" 0xfffff23f 0xd503223f (Outside [])
+ , Encoding "AUTIAZ_HI_hints" 0xfffff23f 0xd503221f (Outside [])
+ , Encoding "AUTIB_64P_dp_1src" 0xfffffc00 0xdac11400 (Outside [(5, OpXSp)])
+ , Encoding "AUTIZB_64Z_dp_1src" 0xffffffe0 0xdac137e0 (Outside [])
+ , Encoding "AUTIB1716_HI_hints" 0xfffff23f 0xd503201f (Outside [])
+ , Encoding "AUTIBSP_HI_hints" 0xfffff23f 0xd503223f (Outside [])
+ , Encoding "AUTIBZ_HI_hints" 0xfffff23f 0xd503221f (Outside [])
+ , Encoding "AXFLAG_M_pstate" 0xfffff0ff 0xd500405f Control
+ , Encoding "B_only_condbranch" 0xff000010 0x54000000 Control
+ , Encoding "B_only_branch_imm" 0xfc000000 0x14000000 Control
+ , Encoding "BC_only_condbranch" 0xff000010 0x54000010 Control
+ , Encoding "BCAX_VVV16_crypto4" 0xffe08000 0xce200000 Covered
+ , Encoding "BFCVT_BS_floatdp1" 0xfffffc00 0x1e634000 (Outside [(5, OpS)])
+ , Encoding "BFCVTN_asimdmisc_4S" 0xbffffc00 0x0ea16800 (Outside [(5, OpV)])
+ , Encoding "BFDOT_asimdelem_E" 0xbfc0f400 0x0f40f000 (Outside [(5, OpV)])
+ , Encoding "BFDOT_asimdsame2_D" 0xbfe0fc00 0x2e40fc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "BFM_32M_bitfield" 0xffc00000 0x33000000 Covered
+ , Encoding "BFM_64M_bitfield" 0xffc00000 0xb3400000 Covered
+ , Encoding "BFMLAL_asimdelem_F" 0xbfc0f400 0x0fc0f000 (Outside [(5, OpV)])
+ , Encoding "BFMLAL_asimdsame2_F_" 0xbfe0fc00 0x2ec0fc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "BFMMLA_asimdsame2_E" 0xffe0fc00 0x6e40ec00
+ (Outside [(0, OpV), (5, OpV), (16, OpV)])
+ , Encoding "BIC_asimdimm_L_hl" 0xbff8cc00 0x2f008400 Covered
+ , Encoding "BIC_asimdimm_L_sl" 0xbff88c00 0x2f000400 Covered
+ , Encoding "BIC_asimdsame_only" 0xbfe0fc00 0x0e601c00 Covered
+ , Encoding "BIC_32_log_shift" 0xff200000 0x0a200000 Covered
+ , Encoding "BIC_64_log_shift" 0xff200000 0x8a200000 Covered
+ , Encoding "BICS_32_log_shift" 0xff200000 0x6a200000 Covered
+ , Encoding "BICS_64_log_shift" 0xff200000 0xea200000 Covered
+ , Encoding "BIF_asimdsame_only" 0xbfe0fc00 0x2ee01c00 Covered
+ , Encoding "BIT_asimdsame_only" 0xbfe0fc00 0x2ea01c00 Covered
+ , Encoding "BL_only_branch_imm" 0xfc000000 0x94000000 Control
+ , Encoding "BLR_64_branch_reg" 0xfffffc1f 0xd63f0000 Control
+ , Encoding "BLRAAZ_64_branch_reg" 0xfffffc1f 0xd63f081f Control
+ , Encoding "BLRAA_64P_branch_reg" 0xfffffc00 0xd73f0800 Control
+ , Encoding "BLRABZ_64_branch_reg" 0xfffffc1f 0xd63f0c1f Control
+ , Encoding "BLRAB_64P_branch_reg" 0xfffffc00 0xd73f0c00 Control
+ , Encoding "BR_64_branch_reg" 0xfffffc1f 0xd61f0000 Control
+ , Encoding "BRAAZ_64_branch_reg" 0xfffffc1f 0xd61f081f Control
+ , Encoding "BRAA_64P_branch_reg" 0xfffffc00 0xd71f0800 Control
+ , Encoding "BRABZ_64_branch_reg" 0xfffffc1f 0xd61f0c1f Control
+ , Encoding "BRAB_64P_branch_reg" 0xfffffc00 0xd71f0c00 Control
+ , Encoding "BRK_EX_exception" 0xffe0001f 0xd4200000 Control
+ , Encoding "BSL_asimdsame_only" 0xbfe0fc00 0x2e601c00 Covered
+ , Encoding "BTI_HB_hints" 0xffffff3f 0xd503241f Control
+ , Encoding "CAS_C32_comswap" 0x7fe0fc00 0x08a07c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASA_C32_comswap" 0x7fe0fc00 0x08e07c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASAL_C32_comswap" 0x7fe0fc00 0x08e0fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASL_C32_comswap" 0x7fe0fc00 0x08a0fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CAS_C64_comswap" 0x7fe0fc00 0x48a07c00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CASA_C64_comswap" 0x7fe0fc00 0x48e07c00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CASAL_C64_comswap" 0x7fe0fc00 0x48e0fc00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CASL_C64_comswap" 0x7fe0fc00 0x48a0fc00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CASAB_C32_comswap" 0xffe0fc00 0x08e07c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASALB_C32_comswap" 0xffe0fc00 0x08e0fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASB_C32_comswap" 0xffe0fc00 0x08a07c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASLB_C32_comswap" 0xffe0fc00 0x08a0fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASAH_C32_comswap" 0xffe0fc00 0x48e07c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASALH_C32_comswap" 0xffe0fc00 0x48e0fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASH_C32_comswap" 0xffe0fc00 0x48a07c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASLH_C32_comswap" 0xffe0fc00 0x48a0fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASP_CP32_comswappr" 0xffe0fc00 0x08207c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASPA_CP32_comswappr" 0xffe0fc00 0x08607c00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASPAL_CP32_comswappr" 0xffe0fc00 0x0860fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASPL_CP32_comswappr" 0xffe0fc00 0x0820fc00
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "CASP_CP64_comswappr" 0xffe0fc00 0x48207c00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CASPA_CP64_comswappr" 0xffe0fc00 0x48607c00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CASPAL_CP64_comswappr" 0xffe0fc00 0x4860fc00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CASPL_CP64_comswappr" 0xffe0fc00 0x4820fc00
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "CBNZ_32_compbranch" 0xff000000 0x35000000 Control
+ , Encoding "CBNZ_64_compbranch" 0xff000000 0xb5000000 Control
+ , Encoding "CBZ_32_compbranch" 0xff000000 0x34000000 Control
+ , Encoding "CBZ_64_compbranch" 0xff000000 0xb4000000 Control
+ , Encoding "CCMN_32_condcmp_imm" 0xffe00c10 0x3a400800 Covered
+ , Encoding "CCMN_64_condcmp_imm" 0xffe00c10 0xba400800 Covered
+ , Encoding "CCMN_32_condcmp_reg" 0xffe00c10 0x3a400000 Covered
+ , Encoding "CCMN_64_condcmp_reg" 0xffe00c10 0xba400000 Covered
+ , Encoding "CCMP_32_condcmp_imm" 0xffe00c10 0x7a400800 Covered
+ , Encoding "CCMP_64_condcmp_imm" 0xffe00c10 0xfa400800 Covered
+ , Encoding "CCMP_32_condcmp_reg" 0xffe00c10 0x7a400000 Covered
+ , Encoding "CCMP_64_condcmp_reg" 0xffe00c10 0xfa400000 Covered
+ , Encoding "CFINV_M_pstate" 0xfffff0ff 0xd500401f Covered
+ , Encoding "CHKFEAT_HI_hints" 0xffffffff 0xd503251f Control
+ , Encoding "CLRBHB_HI_hints" 0xffffffff 0xd50322df Control
+ , Encoding "CLREX_BN_barriers" 0xfffff0ff 0xd503305f Control
+ , Encoding "CLS_asimdmisc_R" 0xbf3ffc00 0x0e204800 Covered
+ , Encoding "CLS_32_dp_1src" 0xfffffc00 0x5ac01400 Covered
+ , Encoding "CLS_64_dp_1src" 0xfffffc00 0xdac01400 Covered
+ , Encoding "CLZ_asimdmisc_R" 0xbf3ffc00 0x2e204800 Covered
+ , Encoding "CLZ_32_dp_1src" 0xfffffc00 0x5ac01000 Covered
+ , Encoding "CLZ_64_dp_1src" 0xfffffc00 0xdac01000 Covered
+ , Encoding "CMEQ_asisdsame_only" 0xff20fc00 0x7e208c00 Covered
+ , Encoding "CMEQ_asimdsame_only" 0xbf20fc00 0x2e208c00 Covered
+ , Encoding "CMEQ_asisdmisc_Z" 0xff3ffc00 0x5e209800 Covered
+ , Encoding "CMEQ_asimdmisc_Z" 0xbf3ffc00 0x0e209800 Covered
+ , Encoding "CMGE_asisdsame_only" 0xff20fc00 0x5e203c00 Covered
+ , Encoding "CMGE_asimdsame_only" 0xbf20fc00 0x0e203c00 Covered
+ , Encoding "CMGE_asisdmisc_Z" 0xff3ffc00 0x7e208800 Covered
+ , Encoding "CMGE_asimdmisc_Z" 0xbf3ffc00 0x2e208800 Covered
+ , Encoding "CMGT_asisdsame_only" 0xff20fc00 0x5e203400 Covered
+ , Encoding "CMGT_asimdsame_only" 0xbf20fc00 0x0e203400 Covered
+ , Encoding "CMGT_asisdmisc_Z" 0xff3ffc00 0x5e208800 Covered
+ , Encoding "CMGT_asimdmisc_Z" 0xbf3ffc00 0x0e208800 Covered
+ , Encoding "CMHI_asisdsame_only" 0xff20fc00 0x7e203400 Covered
+ , Encoding "CMHI_asimdsame_only" 0xbf20fc00 0x2e203400 Covered
+ , Encoding "CMHS_asisdsame_only" 0xff20fc00 0x7e203c00 Covered
+ , Encoding "CMHS_asimdsame_only" 0xbf20fc00 0x2e203c00 Covered
+ , Encoding "CMLE_asisdmisc_Z" 0xff3ffc00 0x7e209800 Covered
+ , Encoding "CMLE_asimdmisc_Z" 0xbf3ffc00 0x2e209800 Covered
+ , Encoding "CMLT_asisdmisc_Z" 0xff3ffc00 0x5e20a800 Covered
+ , Encoding "CMLT_asimdmisc_Z" 0xbf3ffc00 0x0e20a800 Covered
+ , Encoding "CMTST_asisdsame_only" 0xff20fc00 0x5e208c00 Covered
+ , Encoding "CMTST_asimdsame_only" 0xbf20fc00 0x0e208c00 Covered
+ , Encoding "CNT_32_dp_1src" 0xfffffc00 0x5ac01c00 Covered
+ , Encoding "CNT_64_dp_1src" 0xfffffc00 0xdac01c00 Covered
+ , Encoding "CNT_asimdmisc_R" 0xbf3ffc00 0x0e205800 Covered
+ , Encoding "CPYFE_CPY_memcms" 0x3fe0fc00 0x19800400 (Outside [(5, OpX)])
+ , Encoding "CPYFM_CPY_memcms" 0x3fe0fc00 0x19400400 (Outside [(5, OpX)])
+ , Encoding "CPYFP_CPY_memcms" 0x3fe0fc00 0x19000400 (Outside [])
+ , Encoding "CPYFEN_CPY_memcms" 0x3fe0fc00 0x1980c400 (Outside [(5, OpX)])
+ , Encoding "CPYFMN_CPY_memcms" 0x3fe0fc00 0x1940c400 (Outside [(5, OpX)])
+ , Encoding "CPYFPN_CPY_memcms" 0x3fe0fc00 0x1900c400 (Outside [])
+ , Encoding "CPYFERN_CPY_memcms" 0x3fe0fc00 0x19808400 (Outside [(5, OpX)])
+ , Encoding "CPYFMRN_CPY_memcms" 0x3fe0fc00 0x19408400 (Outside [(5, OpX)])
+ , Encoding "CPYFPRN_CPY_memcms" 0x3fe0fc00 0x19008400 (Outside [])
+ , Encoding "CPYFERT_CPY_memcms" 0x3fe0fc00 0x19802400 (Outside [(5, OpX)])
+ , Encoding "CPYFMRT_CPY_memcms" 0x3fe0fc00 0x19402400 (Outside [(5, OpX)])
+ , Encoding "CPYFPRT_CPY_memcms" 0x3fe0fc00 0x19002400 (Outside [])
+ , Encoding "CPYFERTN_CPY_memcms" 0x3fe0fc00 0x1980e400 (Outside [(5, OpX)])
+ , Encoding "CPYFMRTN_CPY_memcms" 0x3fe0fc00 0x1940e400 (Outside [(5, OpX)])
+ , Encoding "CPYFPRTN_CPY_memcms" 0x3fe0fc00 0x1900e400 (Outside [])
+ , Encoding "CPYFERTRN_CPY_memcms" 0x3fe0fc00 0x1980a400 (Outside [(5, OpX)])
+ , Encoding "CPYFMRTRN_CPY_memcms" 0x3fe0fc00 0x1940a400 (Outside [(5, OpX)])
+ , Encoding "CPYFPRTRN_CPY_memcms" 0x3fe0fc00 0x1900a400 (Outside [])
+ , Encoding "CPYFERTWN_CPY_memcms" 0x3fe0fc00 0x19806400 (Outside [(5, OpX)])
+ , Encoding "CPYFMRTWN_CPY_memcms" 0x3fe0fc00 0x19406400 (Outside [(5, OpX)])
+ , Encoding "CPYFPRTWN_CPY_memcms" 0x3fe0fc00 0x19006400 (Outside [])
+ , Encoding "CPYFET_CPY_memcms" 0x3fe0fc00 0x19803400 (Outside [(5, OpX)])
+ , Encoding "CPYFMT_CPY_memcms" 0x3fe0fc00 0x19403400 (Outside [(5, OpX)])
+ , Encoding "CPYFPT_CPY_memcms" 0x3fe0fc00 0x19003400 (Outside [])
+ , Encoding "CPYFETN_CPY_memcms" 0x3fe0fc00 0x1980f400 (Outside [(5, OpX)])
+ , Encoding "CPYFMTN_CPY_memcms" 0x3fe0fc00 0x1940f400 (Outside [(5, OpX)])
+ , Encoding "CPYFPTN_CPY_memcms" 0x3fe0fc00 0x1900f400 (Outside [])
+ , Encoding "CPYFETRN_CPY_memcms" 0x3fe0fc00 0x1980b400 (Outside [(5, OpX)])
+ , Encoding "CPYFMTRN_CPY_memcms" 0x3fe0fc00 0x1940b400 (Outside [(5, OpX)])
+ , Encoding "CPYFPTRN_CPY_memcms" 0x3fe0fc00 0x1900b400 (Outside [])
+ , Encoding "CPYFETWN_CPY_memcms" 0x3fe0fc00 0x19807400 (Outside [(5, OpX)])
+ , Encoding "CPYFMTWN_CPY_memcms" 0x3fe0fc00 0x19407400 (Outside [(5, OpX)])
+ , Encoding "CPYFPTWN_CPY_memcms" 0x3fe0fc00 0x19007400 (Outside [])
+ , Encoding "CPYFEWN_CPY_memcms" 0x3fe0fc00 0x19804400 (Outside [(5, OpX)])
+ , Encoding "CPYFMWN_CPY_memcms" 0x3fe0fc00 0x19404400 (Outside [(5, OpX)])
+ , Encoding "CPYFPWN_CPY_memcms" 0x3fe0fc00 0x19004400 (Outside [])
+ , Encoding "CPYFEWT_CPY_memcms" 0x3fe0fc00 0x19801400 (Outside [(5, OpX)])
+ , Encoding "CPYFMWT_CPY_memcms" 0x3fe0fc00 0x19401400 (Outside [(5, OpX)])
+ , Encoding "CPYFPWT_CPY_memcms" 0x3fe0fc00 0x19001400 (Outside [])
+ , Encoding "CPYFEWTN_CPY_memcms" 0x3fe0fc00 0x1980d400 (Outside [(5, OpX)])
+ , Encoding "CPYFMWTN_CPY_memcms" 0x3fe0fc00 0x1940d400 (Outside [(5, OpX)])
+ , Encoding "CPYFPWTN_CPY_memcms" 0x3fe0fc00 0x1900d400 (Outside [])
+ , Encoding "CPYFEWTRN_CPY_memcms" 0x3fe0fc00 0x19809400 (Outside [(5, OpX)])
+ , Encoding "CPYFMWTRN_CPY_memcms" 0x3fe0fc00 0x19409400 (Outside [(5, OpX)])
+ , Encoding "CPYFPWTRN_CPY_memcms" 0x3fe0fc00 0x19009400 (Outside [])
+ , Encoding "CPYFEWTWN_CPY_memcms" 0x3fe0fc00 0x19805400 (Outside [(5, OpX)])
+ , Encoding "CPYFMWTWN_CPY_memcms" 0x3fe0fc00 0x19405400 (Outside [(5, OpX)])
+ , Encoding "CPYFPWTWN_CPY_memcms" 0x3fe0fc00 0x19005400 (Outside [])
+ , Encoding "CPYE_CPY_memcms" 0x3fe0fc00 0x1d800400 (Outside [(5, OpX)])
+ , Encoding "CPYM_CPY_memcms" 0x3fe0fc00 0x1d400400 (Outside [(5, OpX)])
+ , Encoding "CPYP_CPY_memcms" 0x3fe0fc00 0x1d000400 (Outside [])
+ , Encoding "CPYEN_CPY_memcms" 0x3fe0fc00 0x1d80c400 (Outside [(5, OpX)])
+ , Encoding "CPYMN_CPY_memcms" 0x3fe0fc00 0x1d40c400 (Outside [(5, OpX)])
+ , Encoding "CPYPN_CPY_memcms" 0x3fe0fc00 0x1d00c400 (Outside [])
+ , Encoding "CPYERN_CPY_memcms" 0x3fe0fc00 0x1d808400 (Outside [(5, OpX)])
+ , Encoding "CPYMRN_CPY_memcms" 0x3fe0fc00 0x1d408400 (Outside [(5, OpX)])
+ , Encoding "CPYPRN_CPY_memcms" 0x3fe0fc00 0x1d008400 (Outside [])
+ , Encoding "CPYERT_CPY_memcms" 0x3fe0fc00 0x1d802400 (Outside [(5, OpX)])
+ , Encoding "CPYMRT_CPY_memcms" 0x3fe0fc00 0x1d402400 (Outside [(5, OpX)])
+ , Encoding "CPYPRT_CPY_memcms" 0x3fe0fc00 0x1d002400 (Outside [])
+ , Encoding "CPYERTN_CPY_memcms" 0x3fe0fc00 0x1d80e400 (Outside [(5, OpX)])
+ , Encoding "CPYMRTN_CPY_memcms" 0x3fe0fc00 0x1d40e400 (Outside [(5, OpX)])
+ , Encoding "CPYPRTN_CPY_memcms" 0x3fe0fc00 0x1d00e400 (Outside [])
+ , Encoding "CPYERTRN_CPY_memcms" 0x3fe0fc00 0x1d80a400 (Outside [(5, OpX)])
+ , Encoding "CPYMRTRN_CPY_memcms" 0x3fe0fc00 0x1d40a400 (Outside [(5, OpX)])
+ , Encoding "CPYPRTRN_CPY_memcms" 0x3fe0fc00 0x1d00a400 (Outside [])
+ , Encoding "CPYERTWN_CPY_memcms" 0x3fe0fc00 0x1d806400 (Outside [(5, OpX)])
+ , Encoding "CPYMRTWN_CPY_memcms" 0x3fe0fc00 0x1d406400 (Outside [(5, OpX)])
+ , Encoding "CPYPRTWN_CPY_memcms" 0x3fe0fc00 0x1d006400 (Outside [])
+ , Encoding "CPYET_CPY_memcms" 0x3fe0fc00 0x1d803400 (Outside [(5, OpX)])
+ , Encoding "CPYMT_CPY_memcms" 0x3fe0fc00 0x1d403400 (Outside [(5, OpX)])
+ , Encoding "CPYPT_CPY_memcms" 0x3fe0fc00 0x1d003400 (Outside [])
+ , Encoding "CPYETN_CPY_memcms" 0x3fe0fc00 0x1d80f400 (Outside [(5, OpX)])
+ , Encoding "CPYMTN_CPY_memcms" 0x3fe0fc00 0x1d40f400 (Outside [(5, OpX)])
+ , Encoding "CPYPTN_CPY_memcms" 0x3fe0fc00 0x1d00f400 (Outside [])
+ , Encoding "CPYETRN_CPY_memcms" 0x3fe0fc00 0x1d80b400 (Outside [(5, OpX)])
+ , Encoding "CPYMTRN_CPY_memcms" 0x3fe0fc00 0x1d40b400 (Outside [(5, OpX)])
+ , Encoding "CPYPTRN_CPY_memcms" 0x3fe0fc00 0x1d00b400 (Outside [])
+ , Encoding "CPYETWN_CPY_memcms" 0x3fe0fc00 0x1d807400 (Outside [(5, OpX)])
+ , Encoding "CPYMTWN_CPY_memcms" 0x3fe0fc00 0x1d407400 (Outside [(5, OpX)])
+ , Encoding "CPYPTWN_CPY_memcms" 0x3fe0fc00 0x1d007400 (Outside [])
+ , Encoding "CPYEWN_CPY_memcms" 0x3fe0fc00 0x1d804400 (Outside [(5, OpX)])
+ , Encoding "CPYMWN_CPY_memcms" 0x3fe0fc00 0x1d404400 (Outside [(5, OpX)])
+ , Encoding "CPYPWN_CPY_memcms" 0x3fe0fc00 0x1d004400 (Outside [])
+ , Encoding "CPYEWT_CPY_memcms" 0x3fe0fc00 0x1d801400 (Outside [(5, OpX)])
+ , Encoding "CPYMWT_CPY_memcms" 0x3fe0fc00 0x1d401400 (Outside [(5, OpX)])
+ , Encoding "CPYPWT_CPY_memcms" 0x3fe0fc00 0x1d001400 (Outside [])
+ , Encoding "CPYEWTN_CPY_memcms" 0x3fe0fc00 0x1d80d400 (Outside [(5, OpX)])
+ , Encoding "CPYMWTN_CPY_memcms" 0x3fe0fc00 0x1d40d400 (Outside [(5, OpX)])
+ , Encoding "CPYPWTN_CPY_memcms" 0x3fe0fc00 0x1d00d400 (Outside [])
+ , Encoding "CPYEWTRN_CPY_memcms" 0x3fe0fc00 0x1d809400 (Outside [(5, OpX)])
+ , Encoding "CPYMWTRN_CPY_memcms" 0x3fe0fc00 0x1d409400 (Outside [(5, OpX)])
+ , Encoding "CPYPWTRN_CPY_memcms" 0x3fe0fc00 0x1d009400 (Outside [])
+ , Encoding "CPYEWTWN_CPY_memcms" 0x3fe0fc00 0x1d805400 (Outside [(5, OpX)])
+ , Encoding "CPYMWTWN_CPY_memcms" 0x3fe0fc00 0x1d405400 (Outside [(5, OpX)])
+ , Encoding "CPYPWTWN_CPY_memcms" 0x3fe0fc00 0x1d005400 (Outside [])
+ , Encoding "CRC32B_32C_dp_2src" 0xffe0fc00 0x1ac04000 Covered
+ , Encoding "CRC32H_32C_dp_2src" 0xffe0fc00 0x1ac04400 Covered
+ , Encoding "CRC32W_32C_dp_2src" 0xffe0fc00 0x1ac04800 Covered
+ , Encoding "CRC32X_64C_dp_2src" 0xffe0fc00 0x9ac04c00 Covered
+ , Encoding "CRC32CB_32C_dp_2src" 0xffe0fc00 0x1ac05000 Covered
+ , Encoding "CRC32CH_32C_dp_2src" 0xffe0fc00 0x1ac05400 Covered
+ , Encoding "CRC32CW_32C_dp_2src" 0xffe0fc00 0x1ac05800 Covered
+ , Encoding "CRC32CX_64C_dp_2src" 0xffe0fc00 0x9ac05c00 Covered
+ , Encoding "CSDB_HI_hints" 0xffffffff 0xd503229f Control
+ , Encoding "CSEL_32_condsel" 0xffe00c00 0x1a800000 Covered
+ , Encoding "CSEL_64_condsel" 0xffe00c00 0x9a800000 Covered
+ , Encoding "CSINC_32_condsel" 0xffe00c00 0x1a800400 Covered
+ , Encoding "CSINC_64_condsel" 0xffe00c00 0x9a800400 Covered
+ , Encoding "CSINV_32_condsel" 0xffe00c00 0x5a800000 Covered
+ , Encoding "CSINV_64_condsel" 0xffe00c00 0xda800000 Covered
+ , Encoding "CSNEG_32_condsel" 0xffe00c00 0x5a800400 Covered
+ , Encoding "CSNEG_64_condsel" 0xffe00c00 0xda800400 Covered
+ , Encoding "CTZ_32_dp_1src" 0xfffffc00 0x5ac01800 Covered
+ , Encoding "CTZ_64_dp_1src" 0xfffffc00 0xdac01800 Covered
+ , Encoding "DCPS1_DC_exception" 0xffe0001f 0xd4a00001 Control
+ , Encoding "DCPS2_DC_exception" 0xffe0001f 0xd4a00002 Control
+ , Encoding "DCPS3_DC_exception" 0xffe0001f 0xd4a00003 Control
+ , Encoding "DGH_HI_hints" 0xffffffff 0xd50320df Control
+ , Encoding "DMB_BO_barriers" 0xfffff0ff 0xd50330bf Control
+ , Encoding "DRPS_64E_branch_reg" 0xffffffff 0xd6bf03e0 Control
+ , Encoding "DSB_BO_barriers" 0xfffff0ff 0xd503309f Control
+ , Encoding "DSB_BOn_barriers" 0xfffff3ff 0xd503323f Control
+ , Encoding "DUP_asisdone_only" 0xffe0fc00 0x5e000400 Covered
+ , Encoding "DUP_asimdins_DV_v" 0xbfe0fc00 0x0e000400 Covered
+ , Encoding "DUP_asimdins_DR_r" 0xbfe0fc00 0x0e000c00 Covered
+ , Encoding "EON_32_log_shift" 0xff200000 0x4a200000 Covered
+ , Encoding "EON_64_log_shift" 0xff200000 0xca200000 Covered
+ , Encoding "EOR3_VVV16_crypto4" 0xffe08000 0xce000000 Covered
+ , Encoding "EOR_asimdsame_only" 0xbfe0fc00 0x2e201c00 Covered
+ , Encoding "EOR_32_log_imm" 0xffc00000 0x52000000 Covered
+ , Encoding "EOR_64_log_imm" 0xff800000 0xd2000000 Covered
+ , Encoding "EOR_32_log_shift" 0xff200000 0x4a000000 Covered
+ , Encoding "EOR_64_log_shift" 0xff200000 0xca000000 Covered
+ , Encoding "ERET_64E_branch_reg" 0xffffffff 0xd69f03e0 Control
+ , Encoding "ERETAA_64E_branch_reg" 0xffffffff 0xd69f0bff Control
+ , Encoding "ERETAB_64E_branch_reg" 0xffffffff 0xd69f0fff Control
+ , Encoding "ESB_HI_hints" 0xffffffff 0xd503221f Control
+ , Encoding "EXT_asimdext_only" 0xbfe08400 0x2e000000 Covered
+ , Encoding "EXTR_32_extract" 0xffe08000 0x13800000 Covered
+ , Encoding "EXTR_64_extract" 0xffe00000 0x93c00000 Covered
+ , Encoding "FABD_asisdsamefp16_only" 0xffe0fc00 0x7ec01400
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FABD_asisdsame_only" 0xffa0fc00 0x7ea0d400 (Outside [])
+ , Encoding "FABD_asimdsamefp16_only" 0xbfe0fc00 0x2ec01400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FABD_asimdsame_only" 0xbfa0fc00 0x2ea0d400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FABS_asimdmiscfp16_R" 0xbffffc00 0x0ef8f800 (Outside [(5, OpV)])
+ , Encoding "FABS_asimdmisc_R" 0xbfbffc00 0x0ea0f800 (Outside [(5, OpV)])
+ , Encoding "FABS_H_floatdp1" 0xfffffc00 0x1ee0c000 (Outside [(5, OpH)])
+ , Encoding "FABS_S_floatdp1" 0xfffffc00 0x1e20c000 (Outside [(5, OpS)])
+ , Encoding "FABS_D_floatdp1" 0xfffffc00 0x1e60c000 (Outside [(5, OpD)])
+ , Encoding "FACGE_asisdsamefp16_only" 0xffe0fc00 0x7e402c00
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FACGE_asisdsame_only" 0xffa0fc00 0x7e20ec00 (Outside [])
+ , Encoding "FACGE_asimdsamefp16_only" 0xbfe0fc00 0x2e402c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FACGE_asimdsame_only" 0xbfa0fc00 0x2e20ec00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FACGT_asisdsamefp16_only" 0xffe0fc00 0x7ec02c00
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FACGT_asisdsame_only" 0xffa0fc00 0x7ea0ec00 (Outside [])
+ , Encoding "FACGT_asimdsamefp16_only" 0xbfe0fc00 0x2ec02c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FACGT_asimdsame_only" 0xbfa0fc00 0x2ea0ec00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FADD_asimdsamefp16_only" 0xbfe0fc00 0x0e401400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FADD_asimdsame_only" 0xbfa0fc00 0x0e20d400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FADD_H_floatdp2" 0xffe0fc00 0x1ee02800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FADD_S_floatdp2" 0xffe0fc00 0x1e202800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FADD_D_floatdp2" 0xffe0fc00 0x1e602800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FADDP_asisdpair_only_H" 0xffbffc00 0x5e30d800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FADDP_asisdpair_only_SD" 0xffbffc00 0x7e30d800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FADDP_asimdsamefp16_only" 0xbfe0fc00 0x2e401400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FADDP_asimdsame_only" 0xbfa0fc00 0x2e20d400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCADD_asimdsame2_C" 0xbf20ec00 0x2e00e400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCCMP_H_floatccmp" 0xffe00c10 0x1ee00400
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FCCMP_S_floatccmp" 0xffe00c10 0x1e200400
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FCCMP_D_floatccmp" 0xffe00c10 0x1e600400
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FCCMPE_H_floatccmp" 0xffe00c10 0x1ee00410
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FCCMPE_S_floatccmp" 0xffe00c10 0x1e200410
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FCCMPE_D_floatccmp" 0xffe00c10 0x1e600410
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FCMEQ_asisdsamefp16_only" 0xffe0fc00 0x5e402400
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FCMEQ_asisdsame_only" 0xffa0fc00 0x5e20e400 (Outside [])
+ , Encoding "FCMEQ_asimdsamefp16_only" 0xbfe0fc00 0x0e402400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCMEQ_asimdsame_only" 0xbfa0fc00 0x0e20e400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCMEQ_asisdmiscfp16_FZ" 0xfffffc00 0x5ef8d800
+ (Outside [(5, OpH)])
+ , Encoding "FCMEQ_asisdmisc_FZ" 0xffbffc00 0x5ea0d800 (Outside [])
+ , Encoding "FCMEQ_asimdmiscfp16_FZ" 0xbffffc00 0x0ef8d800
+ (Outside [(5, OpV)])
+ , Encoding "FCMEQ_asimdmisc_FZ" 0xbfbffc00 0x0ea0d800 (Outside [(5, OpV)])
+ , Encoding "FCMGE_asisdsamefp16_only" 0xffe0fc00 0x7e402400
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FCMGE_asisdsame_only" 0xffa0fc00 0x7e20e400 (Outside [])
+ , Encoding "FCMGE_asimdsamefp16_only" 0xbfe0fc00 0x2e402400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCMGE_asimdsame_only" 0xbfa0fc00 0x2e20e400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCMGE_asisdmiscfp16_FZ" 0xfffffc00 0x7ef8c800
+ (Outside [(5, OpH)])
+ , Encoding "FCMGE_asisdmisc_FZ" 0xffbffc00 0x7ea0c800 (Outside [])
+ , Encoding "FCMGE_asimdmiscfp16_FZ" 0xbffffc00 0x2ef8c800
+ (Outside [(5, OpV)])
+ , Encoding "FCMGE_asimdmisc_FZ" 0xbfbffc00 0x2ea0c800 (Outside [(5, OpV)])
+ , Encoding "FCMGT_asisdsamefp16_only" 0xffe0fc00 0x7ec02400
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FCMGT_asisdsame_only" 0xffa0fc00 0x7ea0e400 (Outside [])
+ , Encoding "FCMGT_asimdsamefp16_only" 0xbfe0fc00 0x2ec02400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCMGT_asimdsame_only" 0xbfa0fc00 0x2ea0e400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCMGT_asisdmiscfp16_FZ" 0xfffffc00 0x5ef8c800
+ (Outside [(5, OpH)])
+ , Encoding "FCMGT_asisdmisc_FZ" 0xffbffc00 0x5ea0c800 (Outside [])
+ , Encoding "FCMGT_asimdmiscfp16_FZ" 0xbffffc00 0x0ef8c800
+ (Outside [(5, OpV)])
+ , Encoding "FCMGT_asimdmisc_FZ" 0xbfbffc00 0x0ea0c800 (Outside [(5, OpV)])
+ , Encoding "FCMLA_asimdelem_C_H" 0xbfc09400 0x2f401000 (Outside [(5, OpV)])
+ , Encoding "FCMLA_asimdelem_C_S" 0xbfc09400 0x2f801000 (Outside [(5, OpV)])
+ , Encoding "FCMLA_asimdsame2_C" 0xbf20e400 0x2e00c400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FCMLE_asisdmiscfp16_FZ" 0xfffffc00 0x7ef8d800
+ (Outside [(5, OpH)])
+ , Encoding "FCMLE_asisdmisc_FZ" 0xffbffc00 0x7ea0d800 (Outside [])
+ , Encoding "FCMLE_asimdmiscfp16_FZ" 0xbffffc00 0x2ef8d800
+ (Outside [(5, OpV)])
+ , Encoding "FCMLE_asimdmisc_FZ" 0xbfbffc00 0x2ea0d800 (Outside [(5, OpV)])
+ , Encoding "FCMLT_asisdmiscfp16_FZ" 0xfffffc00 0x5ef8e800
+ (Outside [(5, OpH)])
+ , Encoding "FCMLT_asisdmisc_FZ" 0xffbffc00 0x5ea0e800 (Outside [])
+ , Encoding "FCMLT_asimdmiscfp16_FZ" 0xbffffc00 0x0ef8e800
+ (Outside [(5, OpV)])
+ , Encoding "FCMLT_asimdmisc_FZ" 0xbfbffc00 0x0ea0e800 (Outside [(5, OpV)])
+ , Encoding "FCMP_H_floatcmp" 0xffe0fc0f 0x1ee02000
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FCMP_HZ_floatcmp" 0xffe0fc0f 0x1ee02008 (Outside [(5, OpH)])
+ , Encoding "FCMP_S_floatcmp" 0xffe0fc0f 0x1e202000
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FCMP_SZ_floatcmp" 0xffe0fc0f 0x1e202008 (Outside [(5, OpS)])
+ , Encoding "FCMP_D_floatcmp" 0xffe0fc0f 0x1e602000
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FCMP_DZ_floatcmp" 0xffe0fc0f 0x1e602008 (Outside [(5, OpD)])
+ , Encoding "FCMPE_H_floatcmp" 0xffe0fc0f 0x1ee02000
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FCMPE_HZ_floatcmp" 0xffe0fc0f 0x1ee02008 (Outside [(5, OpH)])
+ , Encoding "FCMPE_S_floatcmp" 0xffe0fc0f 0x1e202000
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FCMPE_SZ_floatcmp" 0xffe0fc0f 0x1e202008 (Outside [(5, OpS)])
+ , Encoding "FCMPE_D_floatcmp" 0xffe0fc0f 0x1e602000
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FCMPE_DZ_floatcmp" 0xffe0fc0f 0x1e602008 (Outside [(5, OpD)])
+ , Encoding "FCSEL_H_floatsel" 0xffe00c00 0x1ee00c00 Covered
+ , Encoding "FCSEL_S_floatsel" 0xffe00c00 0x1e200c00 Covered
+ , Encoding "FCSEL_D_floatsel" 0xffe00c00 0x1e600c00 Covered
+ , Encoding "FCVT_SH_floatdp1" 0xfffffc00 0x1ee24000 (Outside [(5, OpH)])
+ , Encoding "FCVT_DH_floatdp1" 0xfffffc00 0x1ee2c000 (Outside [(5, OpH)])
+ , Encoding "FCVT_HS_floatdp1" 0xfffffc00 0x1e23c000 (Outside [(5, OpS)])
+ , Encoding "FCVT_DS_floatdp1" 0xfffffc00 0x1e22c000 (Outside [(5, OpS)])
+ , Encoding "FCVT_HD_floatdp1" 0xfffffc00 0x1e63c000 (Outside [(5, OpD)])
+ , Encoding "FCVT_SD_floatdp1" 0xfffffc00 0x1e624000 (Outside [(5, OpD)])
+ , Encoding "FCVTAS_asisdmiscfp16_R" 0xfffffc00 0x5e79c800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTAS_asisdmisc_R" 0xffbffc00 0x5e21c800 (Outside [])
+ , Encoding "FCVTAS_asimdmiscfp16_R" 0xbffffc00 0x0e79c800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTAS_asimdmisc_R" 0xbfbffc00 0x0e21c800 (Outside [(5, OpV)])
+ , Encoding "FCVTAS_32H_float2int" 0xfffffc00 0x1ee40000 (Outside [(5, OpH)])
+ , Encoding "FCVTAS_64H_float2int" 0xfffffc00 0x9ee40000 (Outside [(5, OpH)])
+ , Encoding "FCVTAS_32S_float2int" 0xfffffc00 0x1e240000 (Outside [(5, OpS)])
+ , Encoding "FCVTAS_64S_float2int" 0xfffffc00 0x9e240000 (Outside [(5, OpS)])
+ , Encoding "FCVTAS_32D_float2int" 0xfffffc00 0x1e640000 (Outside [(5, OpD)])
+ , Encoding "FCVTAS_64D_float2int" 0xfffffc00 0x9e640000 (Outside [(5, OpD)])
+ , Encoding "FCVTAU_asisdmiscfp16_R" 0xfffffc00 0x7e79c800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTAU_asisdmisc_R" 0xffbffc00 0x7e21c800 (Outside [])
+ , Encoding "FCVTAU_asimdmiscfp16_R" 0xbffffc00 0x2e79c800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTAU_asimdmisc_R" 0xbfbffc00 0x2e21c800 (Outside [(5, OpV)])
+ , Encoding "FCVTAU_32H_float2int" 0xfffffc00 0x1ee50000 (Outside [(5, OpH)])
+ , Encoding "FCVTAU_64H_float2int" 0xfffffc00 0x9ee50000 (Outside [(5, OpH)])
+ , Encoding "FCVTAU_32S_float2int" 0xfffffc00 0x1e250000 (Outside [(5, OpS)])
+ , Encoding "FCVTAU_64S_float2int" 0xfffffc00 0x9e250000 (Outside [(5, OpS)])
+ , Encoding "FCVTAU_32D_float2int" 0xfffffc00 0x1e650000 (Outside [(5, OpD)])
+ , Encoding "FCVTAU_64D_float2int" 0xfffffc00 0x9e650000 (Outside [(5, OpD)])
+ , Encoding "FCVTL_asimdmisc_L" 0xbfbffc00 0x0e217800 (Outside [(5, OpV)])
+ , Encoding "FCVTMS_asisdmiscfp16_R" 0xfffffc00 0x5e79b800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTMS_asisdmisc_R" 0xffbffc00 0x5e21b800 (Outside [])
+ , Encoding "FCVTMS_asimdmiscfp16_R" 0xbffffc00 0x0e79b800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTMS_asimdmisc_R" 0xbfbffc00 0x0e21b800 (Outside [(5, OpV)])
+ , Encoding "FCVTMS_32H_float2int" 0xfffffc00 0x1ef00000 (Outside [(5, OpH)])
+ , Encoding "FCVTMS_64H_float2int" 0xfffffc00 0x9ef00000 (Outside [(5, OpH)])
+ , Encoding "FCVTMS_32S_float2int" 0xfffffc00 0x1e300000 (Outside [(5, OpS)])
+ , Encoding "FCVTMS_64S_float2int" 0xfffffc00 0x9e300000 (Outside [(5, OpS)])
+ , Encoding "FCVTMS_32D_float2int" 0xfffffc00 0x1e700000 (Outside [(5, OpD)])
+ , Encoding "FCVTMS_64D_float2int" 0xfffffc00 0x9e700000 (Outside [(5, OpD)])
+ , Encoding "FCVTMU_asisdmiscfp16_R" 0xfffffc00 0x7e79b800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTMU_asisdmisc_R" 0xffbffc00 0x7e21b800 (Outside [])
+ , Encoding "FCVTMU_asimdmiscfp16_R" 0xbffffc00 0x2e79b800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTMU_asimdmisc_R" 0xbfbffc00 0x2e21b800 (Outside [(5, OpV)])
+ , Encoding "FCVTMU_32H_float2int" 0xfffffc00 0x1ef10000 (Outside [(5, OpH)])
+ , Encoding "FCVTMU_64H_float2int" 0xfffffc00 0x9ef10000 (Outside [(5, OpH)])
+ , Encoding "FCVTMU_32S_float2int" 0xfffffc00 0x1e310000 (Outside [(5, OpS)])
+ , Encoding "FCVTMU_64S_float2int" 0xfffffc00 0x9e310000 (Outside [(5, OpS)])
+ , Encoding "FCVTMU_32D_float2int" 0xfffffc00 0x1e710000 (Outside [(5, OpD)])
+ , Encoding "FCVTMU_64D_float2int" 0xfffffc00 0x9e710000 (Outside [(5, OpD)])
+ , Encoding "FCVTN_asimdmisc_N" 0xbfbffc00 0x0e216800 (Outside [(5, OpV)])
+ , Encoding "FCVTNS_asisdmiscfp16_R" 0xfffffc00 0x5e79a800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTNS_asisdmisc_R" 0xffbffc00 0x5e21a800 (Outside [])
+ , Encoding "FCVTNS_asimdmiscfp16_R" 0xbffffc00 0x0e79a800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTNS_asimdmisc_R" 0xbfbffc00 0x0e21a800 (Outside [(5, OpV)])
+ , Encoding "FCVTNS_32H_float2int" 0xfffffc00 0x1ee00000 (Outside [(5, OpH)])
+ , Encoding "FCVTNS_64H_float2int" 0xfffffc00 0x9ee00000 (Outside [(5, OpH)])
+ , Encoding "FCVTNS_32S_float2int" 0xfffffc00 0x1e200000 (Outside [(5, OpS)])
+ , Encoding "FCVTNS_64S_float2int" 0xfffffc00 0x9e200000 (Outside [(5, OpS)])
+ , Encoding "FCVTNS_32D_float2int" 0xfffffc00 0x1e600000 (Outside [(5, OpD)])
+ , Encoding "FCVTNS_64D_float2int" 0xfffffc00 0x9e600000 (Outside [(5, OpD)])
+ , Encoding "FCVTNU_asisdmiscfp16_R" 0xfffffc00 0x7e79a800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTNU_asisdmisc_R" 0xffbffc00 0x7e21a800 (Outside [])
+ , Encoding "FCVTNU_asimdmiscfp16_R" 0xbffffc00 0x2e79a800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTNU_asimdmisc_R" 0xbfbffc00 0x2e21a800 (Outside [(5, OpV)])
+ , Encoding "FCVTNU_32H_float2int" 0xfffffc00 0x1ee10000 (Outside [(5, OpH)])
+ , Encoding "FCVTNU_64H_float2int" 0xfffffc00 0x9ee10000 (Outside [(5, OpH)])
+ , Encoding "FCVTNU_32S_float2int" 0xfffffc00 0x1e210000 (Outside [(5, OpS)])
+ , Encoding "FCVTNU_64S_float2int" 0xfffffc00 0x9e210000 (Outside [(5, OpS)])
+ , Encoding "FCVTNU_32D_float2int" 0xfffffc00 0x1e610000 (Outside [(5, OpD)])
+ , Encoding "FCVTNU_64D_float2int" 0xfffffc00 0x9e610000 (Outside [(5, OpD)])
+ , Encoding "FCVTPS_asisdmiscfp16_R" 0xfffffc00 0x5ef9a800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTPS_asisdmisc_R" 0xffbffc00 0x5ea1a800 (Outside [])
+ , Encoding "FCVTPS_asimdmiscfp16_R" 0xbffffc00 0x0ef9a800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTPS_asimdmisc_R" 0xbfbffc00 0x0ea1a800 (Outside [(5, OpV)])
+ , Encoding "FCVTPS_32H_float2int" 0xfffffc00 0x1ee80000 (Outside [(5, OpH)])
+ , Encoding "FCVTPS_64H_float2int" 0xfffffc00 0x9ee80000 (Outside [(5, OpH)])
+ , Encoding "FCVTPS_32S_float2int" 0xfffffc00 0x1e280000 (Outside [(5, OpS)])
+ , Encoding "FCVTPS_64S_float2int" 0xfffffc00 0x9e280000 (Outside [(5, OpS)])
+ , Encoding "FCVTPS_32D_float2int" 0xfffffc00 0x1e680000 (Outside [(5, OpD)])
+ , Encoding "FCVTPS_64D_float2int" 0xfffffc00 0x9e680000 (Outside [(5, OpD)])
+ , Encoding "FCVTPU_asisdmiscfp16_R" 0xfffffc00 0x7ef9a800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTPU_asisdmisc_R" 0xffbffc00 0x7ea1a800 (Outside [])
+ , Encoding "FCVTPU_asimdmiscfp16_R" 0xbffffc00 0x2ef9a800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTPU_asimdmisc_R" 0xbfbffc00 0x2ea1a800 (Outside [(5, OpV)])
+ , Encoding "FCVTPU_32H_float2int" 0xfffffc00 0x1ee90000 (Outside [(5, OpH)])
+ , Encoding "FCVTPU_64H_float2int" 0xfffffc00 0x9ee90000 (Outside [(5, OpH)])
+ , Encoding "FCVTPU_32S_float2int" 0xfffffc00 0x1e290000 (Outside [(5, OpS)])
+ , Encoding "FCVTPU_64S_float2int" 0xfffffc00 0x9e290000 (Outside [(5, OpS)])
+ , Encoding "FCVTPU_32D_float2int" 0xfffffc00 0x1e690000 (Outside [(5, OpD)])
+ , Encoding "FCVTPU_64D_float2int" 0xfffffc00 0x9e690000 (Outside [(5, OpD)])
+ , Encoding "FCVTXN_asisdmisc_N" 0xffbffc00 0x7e216800 (Outside [])
+ , Encoding "FCVTXN_asimdmisc_N" 0xbfbffc00 0x2e216800 (Outside [(5, OpV)])
+ , Encoding "FCVTZS_asisdshf_C" 0xff80fc00 0x5f00fc00 (Outside [])
+ , Encoding "FCVTZS_asimdshf_C" 0xbf80fc00 0x0f00fc00 (Outside [(5, OpV)])
+ , Encoding "FCVTZS_asisdmiscfp16_R" 0xfffffc00 0x5ef9b800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTZS_asisdmisc_R" 0xffbffc00 0x5ea1b800 (Outside [])
+ , Encoding "FCVTZS_asimdmiscfp16_R" 0xbffffc00 0x0ef9b800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTZS_asimdmisc_R" 0xbfbffc00 0x0ea1b800 (Outside [(5, OpV)])
+ , Encoding "FCVTZS_32H_float2fix" 0xffff0000 0x1ed80000 (Outside [(5, OpH)])
+ , Encoding "FCVTZS_64H_float2fix" 0xffff0000 0x9ed80000 (Outside [(5, OpH)])
+ , Encoding "FCVTZS_32S_float2fix" 0xffff0000 0x1e180000 (Outside [(5, OpS)])
+ , Encoding "FCVTZS_64S_float2fix" 0xffff0000 0x9e180000 (Outside [(5, OpS)])
+ , Encoding "FCVTZS_32D_float2fix" 0xffff0000 0x1e580000 (Outside [(5, OpD)])
+ , Encoding "FCVTZS_64D_float2fix" 0xffff0000 0x9e580000 (Outside [(5, OpD)])
+ , Encoding "FCVTZS_32H_float2int" 0xfffffc00 0x1ef80000 (Outside [(5, OpH)])
+ , Encoding "FCVTZS_64H_float2int" 0xfffffc00 0x9ef80000 (Outside [(5, OpH)])
+ , Encoding "FCVTZS_32S_float2int" 0xfffffc00 0x1e380000 (Outside [(5, OpS)])
+ , Encoding "FCVTZS_64S_float2int" 0xfffffc00 0x9e380000 (Outside [(5, OpS)])
+ , Encoding "FCVTZS_32D_float2int" 0xfffffc00 0x1e780000 (Outside [(5, OpD)])
+ , Encoding "FCVTZS_64D_float2int" 0xfffffc00 0x9e780000 (Outside [(5, OpD)])
+ , Encoding "FCVTZU_asisdshf_C" 0xff80fc00 0x7f00fc00 (Outside [])
+ , Encoding "FCVTZU_asimdshf_C" 0xbf80fc00 0x2f00fc00 (Outside [(5, OpV)])
+ , Encoding "FCVTZU_asisdmiscfp16_R" 0xfffffc00 0x7ef9b800
+ (Outside [(5, OpH)])
+ , Encoding "FCVTZU_asisdmisc_R" 0xffbffc00 0x7ea1b800 (Outside [])
+ , Encoding "FCVTZU_asimdmiscfp16_R" 0xbffffc00 0x2ef9b800
+ (Outside [(5, OpV)])
+ , Encoding "FCVTZU_asimdmisc_R" 0xbfbffc00 0x2ea1b800 (Outside [(5, OpV)])
+ , Encoding "FCVTZU_32H_float2fix" 0xffff0000 0x1ed90000 (Outside [(5, OpH)])
+ , Encoding "FCVTZU_64H_float2fix" 0xffff0000 0x9ed90000 (Outside [(5, OpH)])
+ , Encoding "FCVTZU_32S_float2fix" 0xffff0000 0x1e190000 (Outside [(5, OpS)])
+ , Encoding "FCVTZU_64S_float2fix" 0xffff0000 0x9e190000 (Outside [(5, OpS)])
+ , Encoding "FCVTZU_32D_float2fix" 0xffff0000 0x1e590000 (Outside [(5, OpD)])
+ , Encoding "FCVTZU_64D_float2fix" 0xffff0000 0x9e590000 (Outside [(5, OpD)])
+ , Encoding "FCVTZU_32H_float2int" 0xfffffc00 0x1ef90000 (Outside [(5, OpH)])
+ , Encoding "FCVTZU_64H_float2int" 0xfffffc00 0x9ef90000 (Outside [(5, OpH)])
+ , Encoding "FCVTZU_32S_float2int" 0xfffffc00 0x1e390000 (Outside [(5, OpS)])
+ , Encoding "FCVTZU_64S_float2int" 0xfffffc00 0x9e390000 (Outside [(5, OpS)])
+ , Encoding "FCVTZU_32D_float2int" 0xfffffc00 0x1e790000 (Outside [(5, OpD)])
+ , Encoding "FCVTZU_64D_float2int" 0xfffffc00 0x9e790000 (Outside [(5, OpD)])
+ , Encoding "FDIV_asimdsamefp16_only" 0xbfe0fc00 0x2e403c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FDIV_asimdsame_only" 0xbfa0fc00 0x2e20fc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FDIV_H_floatdp2" 0xffe0fc00 0x1ee01800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FDIV_S_floatdp2" 0xffe0fc00 0x1e201800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FDIV_D_floatdp2" 0xffe0fc00 0x1e601800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FJCVTZS_32D_float2int" 0xfffffc00 0x1e7e0000 (Outside [(5, OpD)])
+ , Encoding "FMADD_H_floatdp3" 0xffe08000 0x1fc00000
+ (Outside [(5, OpH), (10, OpH), (16, OpH)])
+ , Encoding "FMADD_S_floatdp3" 0xffe08000 0x1f000000
+ (Outside [(5, OpS), (10, OpS), (16, OpS)])
+ , Encoding "FMADD_D_floatdp3" 0xffe08000 0x1f400000
+ (Outside [(5, OpD), (10, OpD), (16, OpD)])
+ , Encoding "FMAX_asimdsamefp16_only" 0xbfe0fc00 0x0e403400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAX_asimdsame_only" 0xbfa0fc00 0x0e20f400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAX_H_floatdp2" 0xffe0fc00 0x1ee04800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FMAX_S_floatdp2" 0xffe0fc00 0x1e204800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FMAX_D_floatdp2" 0xffe0fc00 0x1e604800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FMAXNM_asimdsamefp16_only" 0xbfe0fc00 0x0e400400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAXNM_asimdsame_only" 0xbfa0fc00 0x0e20c400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAXNM_H_floatdp2" 0xffe0fc00 0x1ee06800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FMAXNM_S_floatdp2" 0xffe0fc00 0x1e206800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FMAXNM_D_floatdp2" 0xffe0fc00 0x1e606800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FMAXNMP_asisdpair_only_H" 0xffbffc00 0x5e30c800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMAXNMP_asisdpair_only_SD" 0xffbffc00 0x7e30c800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMAXNMP_asimdsamefp16_only" 0xbfe0fc00 0x2e400400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAXNMP_asimdsame_only" 0xbfa0fc00 0x2e20c400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAXNMV_asimdall_only_H" 0xbffffc00 0x0e30c800
+ (Outside [(5, OpV)])
+ , Encoding "FMAXNMV_asimdall_only_SD" 0xbfbffc00 0x2e30c800
+ (Outside [(5, OpV)])
+ , Encoding "FMAXP_asisdpair_only_H" 0xffbffc00 0x5e30f800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMAXP_asisdpair_only_SD" 0xffbffc00 0x7e30f800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMAXP_asimdsamefp16_only" 0xbfe0fc00 0x2e403400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAXP_asimdsame_only" 0xbfa0fc00 0x2e20f400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMAXV_asimdall_only_H" 0xbffffc00 0x0e30f800 (Outside [(5, OpV)])
+ , Encoding "FMAXV_asimdall_only_SD" 0xbfbffc00 0x2e30f800
+ (Outside [(5, OpV)])
+ , Encoding "FMIN_asimdsamefp16_only" 0xbfe0fc00 0x0ec03400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMIN_asimdsame_only" 0xbfa0fc00 0x0ea0f400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMIN_H_floatdp2" 0xffe0fc00 0x1ee05800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FMIN_S_floatdp2" 0xffe0fc00 0x1e205800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FMIN_D_floatdp2" 0xffe0fc00 0x1e605800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FMINNM_asimdsamefp16_only" 0xbfe0fc00 0x0ec00400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMINNM_asimdsame_only" 0xbfa0fc00 0x0ea0c400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMINNM_H_floatdp2" 0xffe0fc00 0x1ee07800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FMINNM_S_floatdp2" 0xffe0fc00 0x1e207800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FMINNM_D_floatdp2" 0xffe0fc00 0x1e607800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FMINNMP_asisdpair_only_H" 0xffbffc00 0x5eb0c800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMINNMP_asisdpair_only_SD" 0xffbffc00 0x7eb0c800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMINNMP_asimdsamefp16_only" 0xbfe0fc00 0x2ec00400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMINNMP_asimdsame_only" 0xbfa0fc00 0x2ea0c400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMINNMV_asimdall_only_H" 0xbffffc00 0x0eb0c800
+ (Outside [(5, OpV)])
+ , Encoding "FMINNMV_asimdall_only_SD" 0xbfbffc00 0x2eb0c800
+ (Outside [(5, OpV)])
+ , Encoding "FMINP_asisdpair_only_H" 0xffbffc00 0x5eb0f800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMINP_asisdpair_only_SD" 0xffbffc00 0x7eb0f800
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMINP_asimdsamefp16_only" 0xbfe0fc00 0x2ec03400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMINP_asimdsame_only" 0xbfa0fc00 0x2ea0f400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMINV_asimdall_only_H" 0xbffffc00 0x0eb0f800 (Outside [(5, OpV)])
+ , Encoding "FMINV_asimdall_only_SD" 0xbfbffc00 0x2eb0f800
+ (Outside [(5, OpV)])
+ , Encoding "FMLA_asisdelem_RH_H" 0xffc0f400 0x5f001000 (Outside [(5, OpH)])
+ , Encoding "FMLA_asisdelem_R_SD" 0xff80f400 0x5f801000 (Outside [])
+ , Encoding "FMLA_asimdelem_RH_H" 0xbfc0f400 0x0f001000 (Outside [(5, OpV)])
+ , Encoding "FMLA_asimdelem_R_SD" 0xbf80f400 0x0f801000 (Outside [(5, OpV)])
+ , Encoding "FMLA_asimdsamefp16_only" 0xbfe0fc00 0x0e400c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMLA_asimdsame_only" 0xbfa0fc00 0x0e20cc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMLAL_asimdelem_LH" 0xbfc0f400 0x0f800000 (Outside [(5, OpV)])
+ , Encoding "FMLAL2_asimdelem_LH" 0xbfc0f400 0x2f808000 (Outside [(5, OpV)])
+ , Encoding "FMLAL_asimdsame_F" 0xbfe0fc00 0x0e20ec00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMLAL2_asimdsame_F" 0xbfe0fc00 0x2e20cc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMLS_asisdelem_RH_H" 0xffc0f400 0x5f005000 (Outside [(5, OpH)])
+ , Encoding "FMLS_asisdelem_R_SD" 0xff80f400 0x5f805000 (Outside [])
+ , Encoding "FMLS_asimdelem_RH_H" 0xbfc0f400 0x0f005000 (Outside [(5, OpV)])
+ , Encoding "FMLS_asimdelem_R_SD" 0xbf80f400 0x0f805000 (Outside [(5, OpV)])
+ , Encoding "FMLS_asimdsamefp16_only" 0xbfe0fc00 0x0ec00c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMLS_asimdsame_only" 0xbfa0fc00 0x0ea0cc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMLSL_asimdelem_LH" 0xbfc0f400 0x0f804000 (Outside [(5, OpV)])
+ , Encoding "FMLSL2_asimdelem_LH" 0xbfc0f400 0x2f80c000 (Outside [(5, OpV)])
+ , Encoding "FMLSL_asimdsame_F" 0xbfe0fc00 0x0ea0ec00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMLSL2_asimdsame_F" 0xbfe0fc00 0x2ea0cc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMOV_asimdimm_H_h" 0xbff8fc00 0x0f00fc00 (Outside [])
+ , Encoding "FMOV_asimdimm_S_s" 0xbff8fc00 0x0f00f400 (Outside [])
+ , Encoding "FMOV_asimdimm_D2_d" 0xfff8fc00 0x6f00f400 (Outside [])
+ , Encoding "FMOV_H_floatdp1" 0xfffffc00 0x1ee04000 (Outside [(5, OpH)])
+ , Encoding "FMOV_S_floatdp1" 0xfffffc00 0x1e204000 (Outside [(5, OpS)])
+ , Encoding "FMOV_D_floatdp1" 0xfffffc00 0x1e604000 (Outside [(5, OpD)])
+ , Encoding "FMOV_32H_float2int" 0xffe9fc00 0x1ee00000 (Outside [(5, OpH)])
+ , Encoding "FMOV_64H_float2int" 0xffe9fc00 0x9ee00000 (Outside [(5, OpH)])
+ , Encoding "FMOV_H32_float2int" 0xffe9fc00 0x1ee10000 (Outside [(5, OpW)])
+ , Encoding "FMOV_S32_float2int" 0xffe9fc00 0x1e210000 (Outside [(5, OpW)])
+ , Encoding "FMOV_32S_float2int" 0xffe9fc00 0x1e200000 (Outside [(5, OpS)])
+ , Encoding "FMOV_H64_float2int" 0xffe9fc00 0x9ee10000 (Outside [(5, OpX)])
+ , Encoding "FMOV_D64_float2int" 0xffe9fc00 0x9e610000 (Outside [(5, OpX)])
+ , Encoding "FMOV_V64I_float2int" 0xffe9fc00 0x9ea90000 (Outside [(5, OpX)])
+ , Encoding "FMOV_64D_float2int" 0xffe9fc00 0x9e600000 (Outside [(5, OpD)])
+ , Encoding "FMOV_64VX_float2int" 0xffe9fc00 0x9ea80000
+ (Outside [(5, OpVWhole)])
+ , Encoding "FMOV_H_floatimm" 0xffe01fe0 0x1ee01000 (Outside [])
+ , Encoding "FMOV_S_floatimm" 0xffe01fe0 0x1e201000 (Outside [])
+ , Encoding "FMOV_D_floatimm" 0xffe01fe0 0x1e601000 (Outside [])
+ , Encoding "FMSUB_H_floatdp3" 0xffe08000 0x1fc08000
+ (Outside [(5, OpH), (10, OpH), (16, OpH)])
+ , Encoding "FMSUB_S_floatdp3" 0xffe08000 0x1f008000
+ (Outside [(5, OpS), (10, OpS), (16, OpS)])
+ , Encoding "FMSUB_D_floatdp3" 0xffe08000 0x1f408000
+ (Outside [(5, OpD), (10, OpD), (16, OpD)])
+ , Encoding "FMUL_asisdelem_RH_H" 0xffc0f400 0x5f009000 (Outside [(5, OpH)])
+ , Encoding "FMUL_asisdelem_R_SD" 0xff80f400 0x5f809000 (Outside [])
+ , Encoding "FMUL_asimdelem_RH_H" 0xbfc0f400 0x0f009000 (Outside [(5, OpV)])
+ , Encoding "FMUL_asimdelem_R_SD" 0xbf80f400 0x0f809000 (Outside [(5, OpV)])
+ , Encoding "FMUL_asimdsamefp16_only" 0xbfe0fc00 0x2e401c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMUL_asimdsame_only" 0xbfa0fc00 0x2e20dc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMUL_H_floatdp2" 0xffe0fc00 0x1ee00800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FMUL_S_floatdp2" 0xffe0fc00 0x1e200800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FMUL_D_floatdp2" 0xffe0fc00 0x1e600800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FMULX_asisdelem_RH_H" 0xffc0f400 0x7f009000 (Outside [(5, OpH)])
+ , Encoding "FMULX_asisdelem_R_SD" 0xff80f400 0x7f809000 (Outside [])
+ , Encoding "FMULX_asimdelem_RH_H" 0xbfc0f400 0x2f009000 (Outside [(5, OpV)])
+ , Encoding "FMULX_asimdelem_R_SD" 0xbf80f400 0x2f809000 (Outside [(5, OpV)])
+ , Encoding "FMULX_asisdsamefp16_only" 0xffe0fc00 0x5e401c00
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FMULX_asisdsame_only" 0xffa0fc00 0x5e20dc00 (Outside [])
+ , Encoding "FMULX_asimdsamefp16_only" 0xbfe0fc00 0x0e401c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FMULX_asimdsame_only" 0xbfa0fc00 0x0e20dc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FNEG_asimdmiscfp16_R" 0xbffffc00 0x2ef8f800 (Outside [(5, OpV)])
+ , Encoding "FNEG_asimdmisc_R" 0xbfbffc00 0x2ea0f800 (Outside [(5, OpV)])
+ , Encoding "FNEG_H_floatdp1" 0xfffffc00 0x1ee14000 (Outside [(5, OpH)])
+ , Encoding "FNEG_S_floatdp1" 0xfffffc00 0x1e214000 (Outside [(5, OpS)])
+ , Encoding "FNEG_D_floatdp1" 0xfffffc00 0x1e614000 (Outside [(5, OpD)])
+ , Encoding "FNMADD_H_floatdp3" 0xffe08000 0x1fe00000
+ (Outside [(5, OpH), (10, OpH), (16, OpH)])
+ , Encoding "FNMADD_S_floatdp3" 0xffe08000 0x1f200000
+ (Outside [(5, OpS), (10, OpS), (16, OpS)])
+ , Encoding "FNMADD_D_floatdp3" 0xffe08000 0x1f600000
+ (Outside [(5, OpD), (10, OpD), (16, OpD)])
+ , Encoding "FNMSUB_H_floatdp3" 0xffe08000 0x1fe08000
+ (Outside [(5, OpH), (10, OpH), (16, OpH)])
+ , Encoding "FNMSUB_S_floatdp3" 0xffe08000 0x1f208000
+ (Outside [(5, OpS), (10, OpS), (16, OpS)])
+ , Encoding "FNMSUB_D_floatdp3" 0xffe08000 0x1f608000
+ (Outside [(5, OpD), (10, OpD), (16, OpD)])
+ , Encoding "FNMUL_H_floatdp2" 0xffe0fc00 0x1ee08800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FNMUL_S_floatdp2" 0xffe0fc00 0x1e208800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FNMUL_D_floatdp2" 0xffe0fc00 0x1e608800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "FRECPE_asisdmiscfp16_R" 0xfffffc00 0x5ef9d800
+ (Outside [(5, OpH)])
+ , Encoding "FRECPE_asisdmisc_R" 0xffbffc00 0x5ea1d800 (Outside [])
+ , Encoding "FRECPE_asimdmiscfp16_R" 0xbffffc00 0x0ef9d800
+ (Outside [(5, OpV)])
+ , Encoding "FRECPE_asimdmisc_R" 0xbfbffc00 0x0ea1d800 (Outside [(5, OpV)])
+ , Encoding "FRECPS_asisdsamefp16_only" 0xffe0fc00 0x5e403c00
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FRECPS_asisdsame_only" 0xffa0fc00 0x5e20fc00 (Outside [])
+ , Encoding "FRECPS_asimdsamefp16_only" 0xbfe0fc00 0x0e403c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FRECPS_asimdsame_only" 0xbfa0fc00 0x0e20fc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FRECPX_asisdmiscfp16_R" 0xfffffc00 0x5ef9f800
+ (Outside [(5, OpH)])
+ , Encoding "FRECPX_asisdmisc_R" 0xffbffc00 0x5ea1f800 (Outside [])
+ , Encoding "FRINT32X_asimdmisc_R" 0xbfbffc00 0x2e21e800 (Outside [(5, OpV)])
+ , Encoding "FRINT32X_S_floatdp1" 0xff7ffc00 0x1e28c000 (Outside [(5, OpS)])
+ , Encoding "FRINT32X_D_floatdp1" 0xff7ffc00 0x1e68c000 (Outside [(5, OpD)])
+ , Encoding "FRINT32Z_asimdmisc_R" 0xbfbffc00 0x0e21e800 (Outside [(5, OpV)])
+ , Encoding "FRINT32Z_S_floatdp1" 0xff7ffc00 0x1e284000 (Outside [(5, OpS)])
+ , Encoding "FRINT32Z_D_floatdp1" 0xff7ffc00 0x1e684000 (Outside [(5, OpD)])
+ , Encoding "FRINT64X_asimdmisc_R" 0xbfbffc00 0x2e21f800 (Outside [(5, OpV)])
+ , Encoding "FRINT64X_S_floatdp1" 0xff7ffc00 0x1e29c000 (Outside [(5, OpS)])
+ , Encoding "FRINT64X_D_floatdp1" 0xff7ffc00 0x1e69c000 (Outside [(5, OpD)])
+ , Encoding "FRINT64Z_asimdmisc_R" 0xbfbffc00 0x0e21f800 (Outside [(5, OpV)])
+ , Encoding "FRINT64Z_S_floatdp1" 0xff7ffc00 0x1e294000 (Outside [(5, OpS)])
+ , Encoding "FRINT64Z_D_floatdp1" 0xff7ffc00 0x1e694000 (Outside [(5, OpD)])
+ , Encoding "FRINTA_asimdmiscfp16_R" 0xbffffc00 0x2e798800
+ (Outside [(5, OpV)])
+ , Encoding "FRINTA_asimdmisc_R" 0xbfbffc00 0x2e218800 (Outside [(5, OpV)])
+ , Encoding "FRINTA_H_floatdp1" 0xfffffc00 0x1ee64000 (Outside [(5, OpH)])
+ , Encoding "FRINTA_S_floatdp1" 0xfffffc00 0x1e264000 (Outside [(5, OpS)])
+ , Encoding "FRINTA_D_floatdp1" 0xfffffc00 0x1e664000 (Outside [(5, OpD)])
+ , Encoding "FRINTI_asimdmiscfp16_R" 0xbffffc00 0x2ef99800
+ (Outside [(5, OpV)])
+ , Encoding "FRINTI_asimdmisc_R" 0xbfbffc00 0x2ea19800 (Outside [(5, OpV)])
+ , Encoding "FRINTI_H_floatdp1" 0xfffffc00 0x1ee7c000 (Outside [(5, OpH)])
+ , Encoding "FRINTI_S_floatdp1" 0xfffffc00 0x1e27c000 (Outside [(5, OpS)])
+ , Encoding "FRINTI_D_floatdp1" 0xfffffc00 0x1e67c000 (Outside [(5, OpD)])
+ , Encoding "FRINTM_asimdmiscfp16_R" 0xbffffc00 0x0e799800
+ (Outside [(5, OpV)])
+ , Encoding "FRINTM_asimdmisc_R" 0xbfbffc00 0x0e219800 (Outside [(5, OpV)])
+ , Encoding "FRINTM_H_floatdp1" 0xfffffc00 0x1ee54000 (Outside [(5, OpH)])
+ , Encoding "FRINTM_S_floatdp1" 0xfffffc00 0x1e254000 (Outside [(5, OpS)])
+ , Encoding "FRINTM_D_floatdp1" 0xfffffc00 0x1e654000 (Outside [(5, OpD)])
+ , Encoding "FRINTN_asimdmiscfp16_R" 0xbffffc00 0x0e798800
+ (Outside [(5, OpV)])
+ , Encoding "FRINTN_asimdmisc_R" 0xbfbffc00 0x0e218800 (Outside [(5, OpV)])
+ , Encoding "FRINTN_H_floatdp1" 0xfffffc00 0x1ee44000 (Outside [(5, OpH)])
+ , Encoding "FRINTN_S_floatdp1" 0xfffffc00 0x1e244000 (Outside [(5, OpS)])
+ , Encoding "FRINTN_D_floatdp1" 0xfffffc00 0x1e644000 (Outside [(5, OpD)])
+ , Encoding "FRINTP_asimdmiscfp16_R" 0xbffffc00 0x0ef98800
+ (Outside [(5, OpV)])
+ , Encoding "FRINTP_asimdmisc_R" 0xbfbffc00 0x0ea18800 (Outside [(5, OpV)])
+ , Encoding "FRINTP_H_floatdp1" 0xfffffc00 0x1ee4c000 (Outside [(5, OpH)])
+ , Encoding "FRINTP_S_floatdp1" 0xfffffc00 0x1e24c000 (Outside [(5, OpS)])
+ , Encoding "FRINTP_D_floatdp1" 0xfffffc00 0x1e64c000 (Outside [(5, OpD)])
+ , Encoding "FRINTX_asimdmiscfp16_R" 0xbffffc00 0x2e799800
+ (Outside [(5, OpV)])
+ , Encoding "FRINTX_asimdmisc_R" 0xbfbffc00 0x2e219800 (Outside [(5, OpV)])
+ , Encoding "FRINTX_H_floatdp1" 0xfffffc00 0x1ee74000 (Outside [(5, OpH)])
+ , Encoding "FRINTX_S_floatdp1" 0xfffffc00 0x1e274000 (Outside [(5, OpS)])
+ , Encoding "FRINTX_D_floatdp1" 0xfffffc00 0x1e674000 (Outside [(5, OpD)])
+ , Encoding "FRINTZ_asimdmiscfp16_R" 0xbffffc00 0x0ef99800
+ (Outside [(5, OpV)])
+ , Encoding "FRINTZ_asimdmisc_R" 0xbfbffc00 0x0ea19800 (Outside [(5, OpV)])
+ , Encoding "FRINTZ_H_floatdp1" 0xfffffc00 0x1ee5c000 (Outside [(5, OpH)])
+ , Encoding "FRINTZ_S_floatdp1" 0xfffffc00 0x1e25c000 (Outside [(5, OpS)])
+ , Encoding "FRINTZ_D_floatdp1" 0xfffffc00 0x1e65c000 (Outside [(5, OpD)])
+ , Encoding "FRSQRTE_asisdmiscfp16_R" 0xfffffc00 0x7ef9d800
+ (Outside [(5, OpH)])
+ , Encoding "FRSQRTE_asisdmisc_R" 0xffbffc00 0x7ea1d800 (Outside [])
+ , Encoding "FRSQRTE_asimdmiscfp16_R" 0xbffffc00 0x2ef9d800
+ (Outside [(5, OpV)])
+ , Encoding "FRSQRTE_asimdmisc_R" 0xbfbffc00 0x2ea1d800 (Outside [(5, OpV)])
+ , Encoding "FRSQRTS_asisdsamefp16_only" 0xffe0fc00 0x5ec03c00
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FRSQRTS_asisdsame_only" 0xffa0fc00 0x5ea0fc00 (Outside [])
+ , Encoding "FRSQRTS_asimdsamefp16_only" 0xbfe0fc00 0x0ec03c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FRSQRTS_asimdsame_only" 0xbfa0fc00 0x0ea0fc00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FSQRT_asimdmiscfp16_R" 0xbffffc00 0x2ef9f800 (Outside [(5, OpV)])
+ , Encoding "FSQRT_asimdmisc_R" 0xbfbffc00 0x2ea1f800 (Outside [(5, OpV)])
+ , Encoding "FSQRT_H_floatdp1" 0xfffffc00 0x1ee1c000 (Outside [(5, OpH)])
+ , Encoding "FSQRT_S_floatdp1" 0xfffffc00 0x1e21c000 (Outside [(5, OpS)])
+ , Encoding "FSQRT_D_floatdp1" 0xfffffc00 0x1e61c000 (Outside [(5, OpD)])
+ , Encoding "FSUB_asimdsamefp16_only" 0xbfe0fc00 0x0ec01400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FSUB_asimdsame_only" 0xbfa0fc00 0x0ea0d400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "FSUB_H_floatdp2" 0xffe0fc00 0x1ee03800
+ (Outside [(5, OpH), (16, OpH)])
+ , Encoding "FSUB_S_floatdp2" 0xffe0fc00 0x1e203800
+ (Outside [(5, OpS), (16, OpS)])
+ , Encoding "FSUB_D_floatdp2" 0xffe0fc00 0x1e603800
+ (Outside [(5, OpD), (16, OpD)])
+ , Encoding "GCSB_HD_hints" 0xffffffff 0xd503227f Control
+ , Encoding "GCSSTR_64_ldst_gcs" 0xfffffc00 0xd91f0c00 (Outside [(0, OpX)])
+ , Encoding "GCSSTTR_64_ldst_gcs" 0xfffffc00 0xd91f1c00 (Outside [(0, OpX)])
+ , Encoding "GMI_64G_dp_2src" 0xffe0fc00 0x9ac01400
+ (Outside [(5, OpXSp), (16, OpX)])
+ , Encoding "HINT_HM_hints" 0xfffff01f 0xd503201f Control
+ , Encoding "HLT_EX_exception" 0xffe0001f 0xd4400000 Control
+ , Encoding "HVC_EX_exception" 0xffe0001f 0xd4000002 Control
+ , Encoding "INS_asimdins_IV_v" 0xffe08400 0x6e000400 Covered
+ , Encoding "INS_asimdins_IR_r" 0xffe0fc00 0x4e001c00 Covered
+ , Encoding "IRG_64I_dp_2src" 0xffe0fc00 0x9ac01000
+ (Outside [(5, OpXSp), (16, OpX)])
+ , Encoding "ISB_BI_barriers" 0xfffff0ff 0xd50330df Control
+ , Encoding "LD1_asisdlse_R1_1v" 0xbfffd000 0x0c405000 Covered
+ , Encoding "LD1_asisdlse_R2_2v" 0xbfffd000 0x0c408000 Covered
+ , Encoding "LD1_asisdlse_R3_3v" 0xbfffd000 0x0c404000 Covered
+ , Encoding "LD1_asisdlse_R4_4v" 0xbfffd000 0x0c400000 Covered
+ , Encoding "LD1_asisdlsep_I1_i1" 0xbfffd000 0x0cdf5000 Covered
+ , Encoding "LD1_asisdlsep_R1_r1" 0xbfe0d000 0x0cc05000 Covered
+ , Encoding "LD1_asisdlsep_I2_i2" 0xbfffd000 0x0cdf8000 Covered
+ , Encoding "LD1_asisdlsep_R2_r2" 0xbfe0d000 0x0cc08000 Covered
+ , Encoding "LD1_asisdlsep_I3_i3" 0xbfffd000 0x0cdf4000 Covered
+ , Encoding "LD1_asisdlsep_R3_r3" 0xbfe0d000 0x0cc04000 Covered
+ , Encoding "LD1_asisdlsep_I4_i4" 0xbfffd000 0x0cdf0000 Covered
+ , Encoding "LD1_asisdlsep_R4_r4" 0xbfe0d000 0x0cc00000 Covered
+ , Encoding "LD1_asisdlso_B1_1b" 0xbfffc000 0x0d400000 Covered
+ , Encoding "LD1_asisdlso_H1_1h" 0xbfffc400 0x0d404000 Covered
+ , Encoding "LD1_asisdlso_S1_1s" 0xbfffcc00 0x0d408000 Covered
+ , Encoding "LD1_asisdlso_D1_1d" 0xbfffdc00 0x0d408400 Covered
+ , Encoding "LD1_asisdlsop_B1_i1b" 0xbfffc000 0x0ddf0000 Covered
+ , Encoding "LD1_asisdlsop_BX1_r1b" 0xbfe0c000 0x0dc00000 Covered
+ , Encoding "LD1_asisdlsop_H1_i1h" 0xbfffc400 0x0ddf4000 Covered
+ , Encoding "LD1_asisdlsop_HX1_r1h" 0xbfe0c400 0x0dc04000 Covered
+ , Encoding "LD1_asisdlsop_S1_i1s" 0xbfffcc00 0x0ddf8000 Covered
+ , Encoding "LD1_asisdlsop_SX1_r1s" 0xbfe0cc00 0x0dc08000 Covered
+ , Encoding "LD1_asisdlsop_D1_i1d" 0xbfffdc00 0x0ddf8400 Covered
+ , Encoding "LD1_asisdlsop_DX1_r1d" 0xbfe0dc00 0x0dc08400 Covered
+ , Encoding "LD1R_asisdlso_R1" 0xbffff000 0x0d40c000 Covered
+ , Encoding "LD1R_asisdlsop_R1_i" 0xbffff000 0x0ddfc000 Covered
+ , Encoding "LD1R_asisdlsop_RX1_r" 0xbfe0f000 0x0dc0c000 Covered
+ , Encoding "LD2_asisdlse_R2" 0xbffff000 0x0c408000 Covered
+ , Encoding "LD2_asisdlsep_I2_i" 0xbffff000 0x0cdf8000 Covered
+ , Encoding "LD2_asisdlsep_R2_r" 0xbfe0f000 0x0cc08000 Covered
+ , Encoding "LD2_asisdlso_B2_2b" 0xbfffc000 0x0d600000 Covered
+ , Encoding "LD2_asisdlso_H2_2h" 0xbfffc400 0x0d604000 Covered
+ , Encoding "LD2_asisdlso_S2_2s" 0xbfffcc00 0x0d608000 Covered
+ , Encoding "LD2_asisdlso_D2_2d" 0xbfffdc00 0x0d608400 Covered
+ , Encoding "LD2_asisdlsop_B2_i2b" 0xbfffc000 0x0dff0000 Covered
+ , Encoding "LD2_asisdlsop_BX2_r2b" 0xbfe0c000 0x0de00000 Covered
+ , Encoding "LD2_asisdlsop_H2_i2h" 0xbfffc400 0x0dff4000 Covered
+ , Encoding "LD2_asisdlsop_HX2_r2h" 0xbfe0c400 0x0de04000 Covered
+ , Encoding "LD2_asisdlsop_S2_i2s" 0xbfffcc00 0x0dff8000 Covered
+ , Encoding "LD2_asisdlsop_SX2_r2s" 0xbfe0cc00 0x0de08000 Covered
+ , Encoding "LD2_asisdlsop_D2_i2d" 0xbfffdc00 0x0dff8400 Covered
+ , Encoding "LD2_asisdlsop_DX2_r2d" 0xbfe0dc00 0x0de08400 Covered
+ , Encoding "LD2R_asisdlso_R2" 0xbffff000 0x0d60c000 Covered
+ , Encoding "LD2R_asisdlsop_R2_i" 0xbffff000 0x0dffc000 Covered
+ , Encoding "LD2R_asisdlsop_RX2_r" 0xbfe0f000 0x0de0c000 Covered
+ , Encoding "LD3_asisdlse_R3" 0xbffff000 0x0c404000 Covered
+ , Encoding "LD3_asisdlsep_I3_i" 0xbffff000 0x0cdf4000 Covered
+ , Encoding "LD3_asisdlsep_R3_r" 0xbfe0f000 0x0cc04000 Covered
+ , Encoding "LD3_asisdlso_B3_3b" 0xbfffc000 0x0d400000 Covered
+ , Encoding "LD3_asisdlso_H3_3h" 0xbfffc400 0x0d404000 Covered
+ , Encoding "LD3_asisdlso_S3_3s" 0xbfffcc00 0x0d408000 Covered
+ , Encoding "LD3_asisdlso_D3_3d" 0xbfffdc00 0x0d408400 Covered
+ , Encoding "LD3_asisdlsop_B3_i3b" 0xbfffc000 0x0ddf0000 Covered
+ , Encoding "LD3_asisdlsop_BX3_r3b" 0xbfe0c000 0x0dc00000 Covered
+ , Encoding "LD3_asisdlsop_H3_i3h" 0xbfffc400 0x0ddf4000 Covered
+ , Encoding "LD3_asisdlsop_HX3_r3h" 0xbfe0c400 0x0dc04000 Covered
+ , Encoding "LD3_asisdlsop_S3_i3s" 0xbfffcc00 0x0ddf8000 Covered
+ , Encoding "LD3_asisdlsop_SX3_r3s" 0xbfe0cc00 0x0dc08000 Covered
+ , Encoding "LD3_asisdlsop_D3_i3d" 0xbfffdc00 0x0ddf8400 Covered
+ , Encoding "LD3_asisdlsop_DX3_r3d" 0xbfe0dc00 0x0dc08400 Covered
+ , Encoding "LD3R_asisdlso_R3" 0xbffff000 0x0d40e000 Covered
+ , Encoding "LD3R_asisdlsop_R3_i" 0xbffff000 0x0ddfe000 Covered
+ , Encoding "LD3R_asisdlsop_RX3_r" 0xbfe0f000 0x0dc0e000 Covered
+ , Encoding "LD4_asisdlse_R4" 0xbffff000 0x0c400000 Covered
+ , Encoding "LD4_asisdlsep_I4_i" 0xbffff000 0x0cdf0000 Covered
+ , Encoding "LD4_asisdlsep_R4_r" 0xbfe0f000 0x0cc00000 Covered
+ , Encoding "LD4_asisdlso_B4_4b" 0xbfffc000 0x0d600000 Covered
+ , Encoding "LD4_asisdlso_H4_4h" 0xbfffc400 0x0d604000 Covered
+ , Encoding "LD4_asisdlso_S4_4s" 0xbfffcc00 0x0d608000 Covered
+ , Encoding "LD4_asisdlso_D4_4d" 0xbfffdc00 0x0d608400 Covered
+ , Encoding "LD4_asisdlsop_B4_i4b" 0xbfffc000 0x0dff0000 Covered
+ , Encoding "LD4_asisdlsop_BX4_r4b" 0xbfe0c000 0x0de00000 Covered
+ , Encoding "LD4_asisdlsop_H4_i4h" 0xbfffc400 0x0dff4000 Covered
+ , Encoding "LD4_asisdlsop_HX4_r4h" 0xbfe0c400 0x0de04000 Covered
+ , Encoding "LD4_asisdlsop_S4_i4s" 0xbfffcc00 0x0dff8000 Covered
+ , Encoding "LD4_asisdlsop_SX4_r4s" 0xbfe0cc00 0x0de08000 Covered
+ , Encoding "LD4_asisdlsop_D4_i4d" 0xbfffdc00 0x0dff8400 Covered
+ , Encoding "LD4_asisdlsop_DX4_r4d" 0xbfe0dc00 0x0de08400 Covered
+ , Encoding "LD4R_asisdlso_R4" 0xbffff000 0x0d60e000 Covered
+ , Encoding "LD4R_asisdlsop_R4_i" 0xbffff000 0x0dffe000 Covered
+ , Encoding "LD4R_asisdlsop_RX4_r" 0xbfe0f000 0x0de0e000 Covered
+ , Encoding "LD64B_64L_memop" 0xfffffc00 0xf83fd000 (Outside [(0, OpX)])
+ , Encoding "LDADD_32_memop" 0x7fe0fc00 0x38200000 Covered
+ , Encoding "LDADDA_32_memop" 0x7fe0fc00 0x38a00000 Covered
+ , Encoding "LDADDAL_32_memop" 0x7fe0fc00 0x38e00000 Covered
+ , Encoding "LDADDL_32_memop" 0x7fe0fc00 0x38600000 Covered
+ , Encoding "LDADD_64_memop" 0x7fe0fc00 0x78200000 Covered
+ , Encoding "LDADDA_64_memop" 0x7fe0fc00 0x78a00000 Covered
+ , Encoding "LDADDAL_64_memop" 0x7fe0fc00 0x78e00000 Covered
+ , Encoding "LDADDL_64_memop" 0x7fe0fc00 0x78600000 Covered
+ , Encoding "LDADDAB_32_memop" 0xffe0fc00 0x38a00000 Covered
+ , Encoding "LDADDALB_32_memop" 0xffe0fc00 0x38e00000 Covered
+ , Encoding "LDADDB_32_memop" 0xffe0fc00 0x38200000 Covered
+ , Encoding "LDADDLB_32_memop" 0xffe0fc00 0x38600000 Covered
+ , Encoding "LDADDAH_32_memop" 0xffe0fc00 0x78a00000 Covered
+ , Encoding "LDADDALH_32_memop" 0xffe0fc00 0x78e00000 Covered
+ , Encoding "LDADDH_32_memop" 0xffe0fc00 0x78200000 Covered
+ , Encoding "LDADDLH_32_memop" 0xffe0fc00 0x78600000 Covered
+ , Encoding "LDAP1_asisdlso_D1" 0xbffffc00 0x0d418400 Covered
+ , Encoding "LDAPR_32L_memop" 0x7fe0fc00 0x38a0c000 Covered
+ , Encoding "LDAPR_64L_memop" 0x7fe0fc00 0x78a0c000 Covered
+ , Encoding "LDAPR_32L_ldapstl_writeback" 0x7ffffc00 0x19c00800 Covered
+ , Encoding "LDAPR_64L_ldapstl_writeback" 0x7ffffc00 0x59c00800 Covered
+ , Encoding "LDAPRB_32L_memop" 0xffe0fc00 0x38a0c000 Covered
+ , Encoding "LDAPRH_32L_memop" 0xffe0fc00 0x78a0c000 Covered
+ , Encoding "LDAPUR_B_ldapstl_simd" 0xffa00c00 0x1d000800 Covered
+ , Encoding "LDAPUR_H_ldapstl_simd" 0xffa00c00 0x5d000800 Covered
+ , Encoding "LDAPUR_S_ldapstl_simd" 0xffa00c00 0x9d000800 Covered
+ , Encoding "LDAPUR_D_ldapstl_simd" 0xffa00c00 0xdd000800 Covered
+ , Encoding "LDAPUR_Q_ldapstl_simd" 0xffa00c00 0x1d800800 Covered
+ , Encoding "LDAPUR_32_ldapstl_unscaled" 0x7fe00c00 0x19400000 Covered
+ , Encoding "LDAPUR_64_ldapstl_unscaled" 0x7fe00c00 0x59400000 Covered
+ , Encoding "LDAPURB_32_ldapstl_unscaled" 0xffe00c00 0x19400000 Covered
+ , Encoding "LDAPURH_32_ldapstl_unscaled" 0xffe00c00 0x59400000 Covered
+ , Encoding "LDAPURSB_32_ldapstl_unscaled" 0xff600c00 0x19400000 Covered
+ , Encoding "LDAPURSB_64_ldapstl_unscaled" 0xff600c00 0x19000000 Covered
+ , Encoding "LDAPURSH_32_ldapstl_unscaled" 0xff600c00 0x59400000 Covered
+ , Encoding "LDAPURSH_64_ldapstl_unscaled" 0xff600c00 0x59000000 Covered
+ , Encoding "LDAPURSW_64_ldapstl_unscaled" 0xffe00c00 0x99800000 Covered
+ , Encoding "LDAR_LR32_ldstord" 0x7fe08000 0x08c08000 Covered
+ , Encoding "LDAR_LR64_ldstord" 0x7fe08000 0x48c08000 Covered
+ , Encoding "LDARB_LR32_ldstord" 0xffe08000 0x08c08000 Covered
+ , Encoding "LDARH_LR32_ldstord" 0xffe08000 0x48c08000 Covered
+ , Encoding "LDAXP_LP32_ldstexclp" 0xffe08000 0x88608000 Covered
+ , Encoding "LDAXP_LP64_ldstexclp" 0xffe08000 0xc8608000 Covered
+ , Encoding "LDAXR_LR32_ldstexclr" 0x7fe08000 0x08408000 Covered
+ , Encoding "LDAXR_LR64_ldstexclr" 0x7fe08000 0x48408000 Covered
+ , Encoding "LDAXRB_LR32_ldstexclr" 0xffe08000 0x08408000 Covered
+ , Encoding "LDAXRH_LR32_ldstexclr" 0xffe08000 0x48408000 Covered
+ , Encoding "LDCLR_32_memop" 0x7fe0fc00 0x38201000 Covered
+ , Encoding "LDCLRA_32_memop" 0x7fe0fc00 0x38a01000 Covered
+ , Encoding "LDCLRAL_32_memop" 0x7fe0fc00 0x38e01000 Covered
+ , Encoding "LDCLRL_32_memop" 0x7fe0fc00 0x38601000 Covered
+ , Encoding "LDCLR_64_memop" 0x7fe0fc00 0x78201000 Covered
+ , Encoding "LDCLRA_64_memop" 0x7fe0fc00 0x78a01000 Covered
+ , Encoding "LDCLRAL_64_memop" 0x7fe0fc00 0x78e01000 Covered
+ , Encoding "LDCLRL_64_memop" 0x7fe0fc00 0x78601000 Covered
+ , Encoding "LDCLRAB_32_memop" 0xffe0fc00 0x38a01000 Covered
+ , Encoding "LDCLRALB_32_memop" 0xffe0fc00 0x38e01000 Covered
+ , Encoding "LDCLRB_32_memop" 0xffe0fc00 0x38201000 Covered
+ , Encoding "LDCLRLB_32_memop" 0xffe0fc00 0x38601000 Covered
+ , Encoding "LDCLRAH_32_memop" 0xffe0fc00 0x78a01000 Covered
+ , Encoding "LDCLRALH_32_memop" 0xffe0fc00 0x78e01000 Covered
+ , Encoding "LDCLRH_32_memop" 0xffe0fc00 0x78201000 Covered
+ , Encoding "LDCLRLH_32_memop" 0xffe0fc00 0x78601000 Covered
+ , Encoding "LDCLRP_128_memop_128" 0xffe0fc00 0x19201000 Covered
+ , Encoding "LDCLRPA_128_memop_128" 0xffe0fc00 0x19a01000 Covered
+ , Encoding "LDCLRPAL_128_memop_128" 0xffe0fc00 0x19e01000 Covered
+ , Encoding "LDCLRPL_128_memop_128" 0xffe0fc00 0x19601000 Covered
+ , Encoding "LDEOR_32_memop" 0x7fe0fc00 0x38202000 Covered
+ , Encoding "LDEORA_32_memop" 0x7fe0fc00 0x38a02000 Covered
+ , Encoding "LDEORAL_32_memop" 0x7fe0fc00 0x38e02000 Covered
+ , Encoding "LDEORL_32_memop" 0x7fe0fc00 0x38602000 Covered
+ , Encoding "LDEOR_64_memop" 0x7fe0fc00 0x78202000 Covered
+ , Encoding "LDEORA_64_memop" 0x7fe0fc00 0x78a02000 Covered
+ , Encoding "LDEORAL_64_memop" 0x7fe0fc00 0x78e02000 Covered
+ , Encoding "LDEORL_64_memop" 0x7fe0fc00 0x78602000 Covered
+ , Encoding "LDEORAB_32_memop" 0xffe0fc00 0x38a02000 Covered
+ , Encoding "LDEORALB_32_memop" 0xffe0fc00 0x38e02000 Covered
+ , Encoding "LDEORB_32_memop" 0xffe0fc00 0x38202000 Covered
+ , Encoding "LDEORLB_32_memop" 0xffe0fc00 0x38602000 Covered
+ , Encoding "LDEORAH_32_memop" 0xffe0fc00 0x78a02000 Covered
+ , Encoding "LDEORALH_32_memop" 0xffe0fc00 0x78e02000 Covered
+ , Encoding "LDEORH_32_memop" 0xffe0fc00 0x78202000 Covered
+ , Encoding "LDEORLH_32_memop" 0xffe0fc00 0x78602000 Covered
+ , Encoding "LDG_64Loffset_ldsttags" 0xffe00c00 0xd9600000 (Outside [])
+ , Encoding "LDGM_64bulk_ldsttags" 0xfffffc00 0xd9e00000 (Outside [])
+ , Encoding "LDIAPP_32L_ldiappstilp" 0x7fe01c00 0x19401800 Covered
+ , Encoding "LDIAPP_32LE_ldiappstilp" 0x7fe01c00 0x19400800 Covered
+ , Encoding "LDIAPP_64L_ldiappstilp" 0x7fe01c00 0x59401800 Covered
+ , Encoding "LDIAPP_64LS_ldiappstilp" 0x7fe01c00 0x59400800 Covered
+ , Encoding "LDLAR_LR32_ldstord" 0x7fe08000 0x08c00000 Covered
+ , Encoding "LDLAR_LR64_ldstord" 0x7fe08000 0x48c00000 Covered
+ , Encoding "LDLARB_LR32_ldstord" 0xffe08000 0x08c00000 Covered
+ , Encoding "LDLARH_LR32_ldstord" 0xffe08000 0x48c00000 Covered
+ , Encoding "LDNP_S_ldstnapair_offs" 0xffc00000 0x2c400000 Covered
+ , Encoding "LDNP_D_ldstnapair_offs" 0xffc00000 0x6c400000 Covered
+ , Encoding "LDNP_Q_ldstnapair_offs" 0xffc00000 0xac400000 Covered
+ , Encoding "LDNP_32_ldstnapair_offs" 0xbfc00000 0x28400000 Covered
+ , Encoding "LDNP_64_ldstnapair_offs" 0xbfc00000 0xa8400000 Covered
+ , Encoding "LDP_S_ldstpair_post" 0xffc00000 0x2cc00000 Covered
+ , Encoding "LDP_D_ldstpair_post" 0xffc00000 0x6cc00000 Covered
+ , Encoding "LDP_Q_ldstpair_post" 0xffc00000 0xacc00000 Covered
+ , Encoding "LDP_S_ldstpair_pre" 0xffc00000 0x2dc00000 Covered
+ , Encoding "LDP_D_ldstpair_pre" 0xffc00000 0x6dc00000 Covered
+ , Encoding "LDP_Q_ldstpair_pre" 0xffc00000 0xadc00000 Covered
+ , Encoding "LDP_S_ldstpair_off" 0xffc00000 0x2d400000 Covered
+ , Encoding "LDP_D_ldstpair_off" 0xffc00000 0x6d400000 Covered
+ , Encoding "LDP_Q_ldstpair_off" 0xffc00000 0xad400000 Covered
+ , Encoding "LDP_32_ldstpair_post" 0xbfc00000 0x28c00000 Covered
+ , Encoding "LDP_64_ldstpair_post" 0xbfc00000 0xa8c00000 Covered
+ , Encoding "LDP_32_ldstpair_pre" 0xbfc00000 0x29c00000 Covered
+ , Encoding "LDP_64_ldstpair_pre" 0xbfc00000 0xa9c00000 Covered
+ , Encoding "LDP_32_ldstpair_off" 0xbfc00000 0x29400000 Covered
+ , Encoding "LDP_64_ldstpair_off" 0xbfc00000 0xa9400000 Covered
+ , Encoding "LDPSW_64_ldstpair_post" 0xffc00000 0x68c00000 Covered
+ , Encoding "LDPSW_64_ldstpair_pre" 0xffc00000 0x69c00000 Covered
+ , Encoding "LDPSW_64_ldstpair_off" 0xffc00000 0x69400000 Covered
+ , Encoding "LDR_B_ldst_immpost" 0xffa00c00 0x3c000400 Covered
+ , Encoding "LDR_H_ldst_immpost" 0xffa00c00 0x7c000400 Covered
+ , Encoding "LDR_S_ldst_immpost" 0xffa00c00 0xbc000400 Covered
+ , Encoding "LDR_D_ldst_immpost" 0xffa00c00 0xfc000400 Covered
+ , Encoding "LDR_Q_ldst_immpost" 0xffa00c00 0x3c800400 Covered
+ , Encoding "LDR_B_ldst_immpre" 0xffa00c00 0x3c000c00 Covered
+ , Encoding "LDR_H_ldst_immpre" 0xffa00c00 0x7c000c00 Covered
+ , Encoding "LDR_S_ldst_immpre" 0xffa00c00 0xbc000c00 Covered
+ , Encoding "LDR_D_ldst_immpre" 0xffa00c00 0xfc000c00 Covered
+ , Encoding "LDR_Q_ldst_immpre" 0xffa00c00 0x3c800c00 Covered
+ , Encoding "LDR_B_ldst_pos" 0xff800000 0x3d000000 Covered
+ , Encoding "LDR_H_ldst_pos" 0xff800000 0x7d000000 Covered
+ , Encoding "LDR_S_ldst_pos" 0xff800000 0xbd000000 Covered
+ , Encoding "LDR_D_ldst_pos" 0xff800000 0xfd000000 Covered
+ , Encoding "LDR_Q_ldst_pos" 0xff800000 0x3d800000 Covered
+ , Encoding "LDR_32_ldst_immpost" 0x7fe00c00 0x38400400 Covered
+ , Encoding "LDR_64_ldst_immpost" 0x7fe00c00 0x78400400 Covered
+ , Encoding "LDR_32_ldst_immpre" 0x7fe00c00 0x38400c00 Covered
+ , Encoding "LDR_64_ldst_immpre" 0x7fe00c00 0x78400c00 Covered
+ , Encoding "LDR_32_ldst_pos" 0x7fc00000 0x39400000 Covered
+ , Encoding "LDR_64_ldst_pos" 0x7fc00000 0x79400000 Covered
+ , Encoding "LDR_S_loadlit" 0xff000000 0x1c000000 Covered
+ , Encoding "LDR_D_loadlit" 0xff000000 0x5c000000 Covered
+ , Encoding "LDR_Q_loadlit" 0xff000000 0x9c000000 Covered
+ , Encoding "LDR_32_loadlit" 0x7f000000 0x18000000 Covered
+ , Encoding "LDR_64_loadlit" 0x7f000000 0x58000000 Covered
+ , Encoding "LDR_B_ldst_regoff" 0xffa00c00 0x3c200800 Covered
+ , Encoding "LDR_BL_ldst_regoff" 0xffa0ec00 0x3c206800 Covered
+ , Encoding "LDR_H_ldst_regoff" 0xffa00c00 0x7c200800 Covered
+ , Encoding "LDR_S_ldst_regoff" 0xffa00c00 0xbc200800 Covered
+ , Encoding "LDR_D_ldst_regoff" 0xffa00c00 0xfc200800 Covered
+ , Encoding "LDR_Q_ldst_regoff" 0xffa00c00 0x3ca00800 Covered
+ , Encoding "LDR_32_ldst_regoff" 0x7fe00c00 0x38600800 Covered
+ , Encoding "LDR_64_ldst_regoff" 0x7fe00c00 0x78600800 Covered
+ , Encoding "LDRAA_64_ldst_pac" 0xffa00c00 0xf8200400 Covered
+ , Encoding "LDRAA_64W_ldst_pac" 0xffa00c00 0xf8200c00 Covered
+ , Encoding "LDRAB_64_ldst_pac" 0xffa00c00 0xf8a00400 Covered
+ , Encoding "LDRAB_64W_ldst_pac" 0xffa00c00 0xf8a00c00 Covered
+ , Encoding "LDRB_32_ldst_immpost" 0xffe00c00 0x38400400 Covered
+ , Encoding "LDRB_32_ldst_immpre" 0xffe00c00 0x38400c00 Covered
+ , Encoding "LDRB_32_ldst_pos" 0xffc00000 0x39400000 Covered
+ , Encoding "LDRB_32B_ldst_regoff" 0xffe00c00 0x38600800 Covered
+ , Encoding "LDRB_32BL_ldst_regoff" 0xffe0ec00 0x38606800 Covered
+ , Encoding "LDRH_32_ldst_immpost" 0xffe00c00 0x78400400 Covered
+ , Encoding "LDRH_32_ldst_immpre" 0xffe00c00 0x78400c00 Covered
+ , Encoding "LDRH_32_ldst_pos" 0xffc00000 0x79400000 Covered
+ , Encoding "LDRH_32_ldst_regoff" 0xffe00c00 0x78600800 Covered
+ , Encoding "LDRSB_32_ldst_immpost" 0xff600c00 0x38400400 Covered
+ , Encoding "LDRSB_64_ldst_immpost" 0xff600c00 0x38000400 Covered
+ , Encoding "LDRSB_32_ldst_immpre" 0xff600c00 0x38400c00 Covered
+ , Encoding "LDRSB_64_ldst_immpre" 0xff600c00 0x38000c00 Covered
+ , Encoding "LDRSB_32_ldst_pos" 0xff400000 0x39400000 Covered
+ , Encoding "LDRSB_64_ldst_pos" 0xff400000 0x39000000 Covered
+ , Encoding "LDRSB_32B_ldst_regoff" 0xff600c00 0x38600800 Covered
+ , Encoding "LDRSB_32BL_ldst_regoff" 0xff60ec00 0x38606800 Covered
+ , Encoding "LDRSB_64B_ldst_regoff" 0xff600c00 0x38200800 Covered
+ , Encoding "LDRSB_64BL_ldst_regoff" 0xff60ec00 0x38206800 Covered
+ , Encoding "LDRSH_32_ldst_immpost" 0xff600c00 0x78400400 Covered
+ , Encoding "LDRSH_64_ldst_immpost" 0xff600c00 0x78000400 Covered
+ , Encoding "LDRSH_32_ldst_immpre" 0xff600c00 0x78400c00 Covered
+ , Encoding "LDRSH_64_ldst_immpre" 0xff600c00 0x78000c00 Covered
+ , Encoding "LDRSH_32_ldst_pos" 0xff400000 0x79400000 Covered
+ , Encoding "LDRSH_64_ldst_pos" 0xff400000 0x79000000 Covered
+ , Encoding "LDRSH_32_ldst_regoff" 0xff600c00 0x78600800 Covered
+ , Encoding "LDRSH_64_ldst_regoff" 0xff600c00 0x78200800 Covered
+ , Encoding "LDRSW_64_ldst_immpost" 0xffe00c00 0xb8800400 Covered
+ , Encoding "LDRSW_64_ldst_immpre" 0xffe00c00 0xb8800c00 Covered
+ , Encoding "LDRSW_64_ldst_pos" 0xffc00000 0xb9800000 Covered
+ , Encoding "LDRSW_64_loadlit" 0xff000000 0x98000000 Covered
+ , Encoding "LDRSW_64_ldst_regoff" 0xffe00c00 0xb8a00800 Covered
+ , Encoding "LDSET_32_memop" 0x7fe0fc00 0x38203000 Covered
+ , Encoding "LDSETA_32_memop" 0x7fe0fc00 0x38a03000 Covered
+ , Encoding "LDSETAL_32_memop" 0x7fe0fc00 0x38e03000 Covered
+ , Encoding "LDSETL_32_memop" 0x7fe0fc00 0x38603000 Covered
+ , Encoding "LDSET_64_memop" 0x7fe0fc00 0x78203000 Covered
+ , Encoding "LDSETA_64_memop" 0x7fe0fc00 0x78a03000 Covered
+ , Encoding "LDSETAL_64_memop" 0x7fe0fc00 0x78e03000 Covered
+ , Encoding "LDSETL_64_memop" 0x7fe0fc00 0x78603000 Covered
+ , Encoding "LDSETAB_32_memop" 0xffe0fc00 0x38a03000 Covered
+ , Encoding "LDSETALB_32_memop" 0xffe0fc00 0x38e03000 Covered
+ , Encoding "LDSETB_32_memop" 0xffe0fc00 0x38203000 Covered
+ , Encoding "LDSETLB_32_memop" 0xffe0fc00 0x38603000 Covered
+ , Encoding "LDSETAH_32_memop" 0xffe0fc00 0x78a03000 Covered
+ , Encoding "LDSETALH_32_memop" 0xffe0fc00 0x78e03000 Covered
+ , Encoding "LDSETH_32_memop" 0xffe0fc00 0x78203000 Covered
+ , Encoding "LDSETLH_32_memop" 0xffe0fc00 0x78603000 Covered
+ , Encoding "LDSETP_128_memop_128" 0xffe0fc00 0x19203000 Covered
+ , Encoding "LDSETPA_128_memop_128" 0xffe0fc00 0x19a03000 Covered
+ , Encoding "LDSETPAL_128_memop_128" 0xffe0fc00 0x19e03000 Covered
+ , Encoding "LDSETPL_128_memop_128" 0xffe0fc00 0x19603000 Covered
+ , Encoding "LDSMAX_32_memop" 0x7fe0fc00 0x38204000 Covered
+ , Encoding "LDSMAXA_32_memop" 0x7fe0fc00 0x38a04000 Covered
+ , Encoding "LDSMAXAL_32_memop" 0x7fe0fc00 0x38e04000 Covered
+ , Encoding "LDSMAXL_32_memop" 0x7fe0fc00 0x38604000 Covered
+ , Encoding "LDSMAX_64_memop" 0x7fe0fc00 0x78204000 Covered
+ , Encoding "LDSMAXA_64_memop" 0x7fe0fc00 0x78a04000 Covered
+ , Encoding "LDSMAXAL_64_memop" 0x7fe0fc00 0x78e04000 Covered
+ , Encoding "LDSMAXL_64_memop" 0x7fe0fc00 0x78604000 Covered
+ , Encoding "LDSMAXAB_32_memop" 0xffe0fc00 0x38a04000 Covered
+ , Encoding "LDSMAXALB_32_memop" 0xffe0fc00 0x38e04000 Covered
+ , Encoding "LDSMAXB_32_memop" 0xffe0fc00 0x38204000 Covered
+ , Encoding "LDSMAXLB_32_memop" 0xffe0fc00 0x38604000 Covered
+ , Encoding "LDSMAXAH_32_memop" 0xffe0fc00 0x78a04000 Covered
+ , Encoding "LDSMAXALH_32_memop" 0xffe0fc00 0x78e04000 Covered
+ , Encoding "LDSMAXH_32_memop" 0xffe0fc00 0x78204000 Covered
+ , Encoding "LDSMAXLH_32_memop" 0xffe0fc00 0x78604000 Covered
+ , Encoding "LDSMIN_32_memop" 0x7fe0fc00 0x38205000 Covered
+ , Encoding "LDSMINA_32_memop" 0x7fe0fc00 0x38a05000 Covered
+ , Encoding "LDSMINAL_32_memop" 0x7fe0fc00 0x38e05000 Covered
+ , Encoding "LDSMINL_32_memop" 0x7fe0fc00 0x38605000 Covered
+ , Encoding "LDSMIN_64_memop" 0x7fe0fc00 0x78205000 Covered
+ , Encoding "LDSMINA_64_memop" 0x7fe0fc00 0x78a05000 Covered
+ , Encoding "LDSMINAL_64_memop" 0x7fe0fc00 0x78e05000 Covered
+ , Encoding "LDSMINL_64_memop" 0x7fe0fc00 0x78605000 Covered
+ , Encoding "LDSMINAB_32_memop" 0xffe0fc00 0x38a05000 Covered
+ , Encoding "LDSMINALB_32_memop" 0xffe0fc00 0x38e05000 Covered
+ , Encoding "LDSMINB_32_memop" 0xffe0fc00 0x38205000 Covered
+ , Encoding "LDSMINLB_32_memop" 0xffe0fc00 0x38605000 Covered
+ , Encoding "LDSMINAH_32_memop" 0xffe0fc00 0x78a05000 Covered
+ , Encoding "LDSMINALH_32_memop" 0xffe0fc00 0x78e05000 Covered
+ , Encoding "LDSMINH_32_memop" 0xffe0fc00 0x78205000 Covered
+ , Encoding "LDSMINLH_32_memop" 0xffe0fc00 0x78605000 Covered
+ , Encoding "LDTR_32_ldst_unpriv" 0x7fe00c00 0x38400800 Covered
+ , Encoding "LDTR_64_ldst_unpriv" 0x7fe00c00 0x78400800 Covered
+ , Encoding "LDTRB_32_ldst_unpriv" 0xffe00c00 0x38400800 Covered
+ , Encoding "LDTRH_32_ldst_unpriv" 0xffe00c00 0x78400800 Covered
+ , Encoding "LDTRSB_32_ldst_unpriv" 0xff600c00 0x38400800 Covered
+ , Encoding "LDTRSB_64_ldst_unpriv" 0xff600c00 0x38000800 Covered
+ , Encoding "LDTRSH_32_ldst_unpriv" 0xff600c00 0x78400800 Covered
+ , Encoding "LDTRSH_64_ldst_unpriv" 0xff600c00 0x78000800 Covered
+ , Encoding "LDTRSW_64_ldst_unpriv" 0xffe00c00 0xb8800800 Covered
+ , Encoding "LDUMAX_32_memop" 0x7fe0fc00 0x38206000 Covered
+ , Encoding "LDUMAXA_32_memop" 0x7fe0fc00 0x38a06000 Covered
+ , Encoding "LDUMAXAL_32_memop" 0x7fe0fc00 0x38e06000 Covered
+ , Encoding "LDUMAXL_32_memop" 0x7fe0fc00 0x38606000 Covered
+ , Encoding "LDUMAX_64_memop" 0x7fe0fc00 0x78206000 Covered
+ , Encoding "LDUMAXA_64_memop" 0x7fe0fc00 0x78a06000 Covered
+ , Encoding "LDUMAXAL_64_memop" 0x7fe0fc00 0x78e06000 Covered
+ , Encoding "LDUMAXL_64_memop" 0x7fe0fc00 0x78606000 Covered
+ , Encoding "LDUMAXAB_32_memop" 0xffe0fc00 0x38a06000 Covered
+ , Encoding "LDUMAXALB_32_memop" 0xffe0fc00 0x38e06000 Covered
+ , Encoding "LDUMAXB_32_memop" 0xffe0fc00 0x38206000 Covered
+ , Encoding "LDUMAXLB_32_memop" 0xffe0fc00 0x38606000 Covered
+ , Encoding "LDUMAXAH_32_memop" 0xffe0fc00 0x78a06000 Covered
+ , Encoding "LDUMAXALH_32_memop" 0xffe0fc00 0x78e06000 Covered
+ , Encoding "LDUMAXH_32_memop" 0xffe0fc00 0x78206000 Covered
+ , Encoding "LDUMAXLH_32_memop" 0xffe0fc00 0x78606000 Covered
+ , Encoding "LDUMIN_32_memop" 0x7fe0fc00 0x38207000 Covered
+ , Encoding "LDUMINA_32_memop" 0x7fe0fc00 0x38a07000 Covered
+ , Encoding "LDUMINAL_32_memop" 0x7fe0fc00 0x38e07000 Covered
+ , Encoding "LDUMINL_32_memop" 0x7fe0fc00 0x38607000 Covered
+ , Encoding "LDUMIN_64_memop" 0x7fe0fc00 0x78207000 Covered
+ , Encoding "LDUMINA_64_memop" 0x7fe0fc00 0x78a07000 Covered
+ , Encoding "LDUMINAL_64_memop" 0x7fe0fc00 0x78e07000 Covered
+ , Encoding "LDUMINL_64_memop" 0x7fe0fc00 0x78607000 Covered
+ , Encoding "LDUMINAB_32_memop" 0xffe0fc00 0x38a07000 Covered
+ , Encoding "LDUMINALB_32_memop" 0xffe0fc00 0x38e07000 Covered
+ , Encoding "LDUMINB_32_memop" 0xffe0fc00 0x38207000 Covered
+ , Encoding "LDUMINLB_32_memop" 0xffe0fc00 0x38607000 Covered
+ , Encoding "LDUMINAH_32_memop" 0xffe0fc00 0x78a07000 Covered
+ , Encoding "LDUMINALH_32_memop" 0xffe0fc00 0x78e07000 Covered
+ , Encoding "LDUMINH_32_memop" 0xffe0fc00 0x78207000 Covered
+ , Encoding "LDUMINLH_32_memop" 0xffe0fc00 0x78607000 Covered
+ , Encoding "LDUR_B_ldst_unscaled" 0xffa00c00 0x3c000000 Covered
+ , Encoding "LDUR_H_ldst_unscaled" 0xffa00c00 0x7c000000 Covered
+ , Encoding "LDUR_S_ldst_unscaled" 0xffa00c00 0xbc000000 Covered
+ , Encoding "LDUR_D_ldst_unscaled" 0xffa00c00 0xfc000000 Covered
+ , Encoding "LDUR_Q_ldst_unscaled" 0xffa00c00 0x3c800000 Covered
+ , Encoding "LDUR_32_ldst_unscaled" 0x7fe00c00 0x38400000 Covered
+ , Encoding "LDUR_64_ldst_unscaled" 0x7fe00c00 0x78400000 Covered
+ , Encoding "LDURB_32_ldst_unscaled" 0xffe00c00 0x38400000 Covered
+ , Encoding "LDURH_32_ldst_unscaled" 0xffe00c00 0x78400000 Covered
+ , Encoding "LDURSB_32_ldst_unscaled" 0xff600c00 0x38400000 Covered
+ , Encoding "LDURSB_64_ldst_unscaled" 0xff600c00 0x38000000 Covered
+ , Encoding "LDURSH_32_ldst_unscaled" 0xff600c00 0x78400000 Covered
+ , Encoding "LDURSH_64_ldst_unscaled" 0xff600c00 0x78000000 Covered
+ , Encoding "LDURSW_64_ldst_unscaled" 0xffe00c00 0xb8800000 Covered
+ , Encoding "LDXP_LP32_ldstexclp" 0xffe08000 0x88600000 Covered
+ , Encoding "LDXP_LP64_ldstexclp" 0xffe08000 0xc8600000 Covered
+ , Encoding "LDXR_LR32_ldstexclr" 0x7fe08000 0x08400000 Covered
+ , Encoding "LDXR_LR64_ldstexclr" 0x7fe08000 0x48400000 Covered
+ , Encoding "LDXRB_LR32_ldstexclr" 0xffe08000 0x08400000 Covered
+ , Encoding "LDXRH_LR32_ldstexclr" 0xffe08000 0x48400000 Covered
+ , Encoding "LSLV_32_dp_2src" 0xffe0fc00 0x1ac02000 Covered
+ , Encoding "LSLV_64_dp_2src" 0xffe0fc00 0x9ac02000 Covered
+ , Encoding "LSRV_32_dp_2src" 0xffe0fc00 0x1ac02400 Covered
+ , Encoding "LSRV_64_dp_2src" 0xffe0fc00 0x9ac02400 Covered
+ , Encoding "MADD_32A_dp_3src" 0xffe08000 0x1b000000 Covered
+ , Encoding "MADD_64A_dp_3src" 0xffe08000 0x9b000000 Covered
+ , Encoding "MLA_asimdelem_R" 0xbf00f400 0x2f000000 Covered
+ , Encoding "MLA_asimdsame_only" 0xbf20fc00 0x0e209400 Covered
+ , Encoding "MLS_asimdelem_R" 0xbf00f400 0x2f004000 Covered
+ , Encoding "MLS_asimdsame_only" 0xbf20fc00 0x2e209400 Covered
+ , Encoding "MOVI_asimdimm_N_b" 0xbff8fc00 0x0f00e400 Covered
+ , Encoding "MOVI_asimdimm_L_hl" 0xbff8dc00 0x0f008400 Covered
+ , Encoding "MOVI_asimdimm_L_sl" 0xbff89c00 0x0f000400 Covered
+ , Encoding "MOVI_asimdimm_M_sm" 0xbff8ec00 0x0f00c400 Covered
+ , Encoding "MOVI_asimdimm_D_ds" 0xfff8fc00 0x2f00e400 Covered
+ , Encoding "MOVI_asimdimm_D2_d" 0xfff8fc00 0x6f00e400 Covered
+ , Encoding "MOVK_32_movewide" 0xffc00000 0x72800000 Covered
+ , Encoding "MOVK_64_movewide" 0xff800000 0xf2800000 Covered
+ , Encoding "MOVN_32_movewide" 0xffc00000 0x12800000 Covered
+ , Encoding "MOVN_64_movewide" 0xff800000 0x92800000 Covered
+ , Encoding "MOVZ_32_movewide" 0xffc00000 0x52800000 Covered
+ , Encoding "MOVZ_64_movewide" 0xff800000 0xd2800000 Covered
+ , Encoding "MRRS_RS_systemmovepr" 0xfff00000 0xd5700000 Control
+ , Encoding "MRS_RS_systemmove" 0xfff00000 0xd5300000 Control
+ , Encoding "MSR_SI_pstate" 0xfff8f01f 0xd500401f Control
+ , Encoding "MSR_SR_systemmove" 0xfff00000 0xd5100000 Control
+ , Encoding "MSRR_SR_systemmovepr" 0xfff00000 0xd5500000 Control
+ , Encoding "MSUB_32A_dp_3src" 0xffe08000 0x1b008000 Covered
+ , Encoding "MSUB_64A_dp_3src" 0xffe08000 0x9b008000 Covered
+ , Encoding "MUL_asimdelem_R" 0xbf00f400 0x0f008000 Covered
+ , Encoding "MUL_asimdsame_only" 0xbf20fc00 0x0e209c00 Covered
+ , Encoding "MVNI_asimdimm_L_hl" 0xbff8dc00 0x2f008400 Covered
+ , Encoding "MVNI_asimdimm_L_sl" 0xbff89c00 0x2f000400 Covered
+ , Encoding "MVNI_asimdimm_M_sm" 0xbff8ec00 0x2f00c400 Covered
+ , Encoding "NEG_asisdmisc_R" 0xff3ffc00 0x7e20b800 Covered
+ , Encoding "NEG_asimdmisc_R" 0xbf3ffc00 0x2e20b800 Covered
+ , Encoding "NOP_HI_hints" 0xffffffff 0xd503201f Covered
+ , Encoding "NOT_asimdmisc_R" 0xbffffc00 0x2e205800 Covered
+ , Encoding "ORN_asimdsame_only" 0xbfe0fc00 0x0ee01c00 Covered
+ , Encoding "ORN_32_log_shift" 0xff200000 0x2a200000 Covered
+ , Encoding "ORN_64_log_shift" 0xff200000 0xaa200000 Covered
+ , Encoding "ORR_asimdimm_L_hl" 0xbff8cc00 0x0f008400 Covered
+ , Encoding "ORR_asimdimm_L_sl" 0xbff88c00 0x0f000400 Covered
+ , Encoding "ORR_asimdsame_only" 0xbfe0fc00 0x0ea01c00 Covered
+ , Encoding "ORR_32_log_imm" 0xffc00000 0x32000000 Covered
+ , Encoding "ORR_64_log_imm" 0xff800000 0xb2000000 Covered
+ , Encoding "ORR_32_log_shift" 0xff200000 0x2a000000 Covered
+ , Encoding "ORR_64_log_shift" 0xff200000 0xaa000000 Covered
+ , Encoding "PACDA_64P_dp_1src" 0xfffffc00 0xdac10800 (Outside [(5, OpXSp)])
+ , Encoding "PACDZA_64Z_dp_1src" 0xffffffe0 0xdac12be0 (Outside [])
+ , Encoding "PACDB_64P_dp_1src" 0xfffffc00 0xdac10c00 (Outside [(5, OpXSp)])
+ , Encoding "PACDZB_64Z_dp_1src" 0xffffffe0 0xdac12fe0 (Outside [])
+ , Encoding "PACGA_64P_dp_2src" 0xffe0fc00 0x9ac03000
+ (Outside [(5, OpX), (16, OpXSp)])
+ , Encoding "PACIA_64P_dp_1src" 0xfffffc00 0xdac10000 (Outside [(5, OpXSp)])
+ , Encoding "PACIZA_64Z_dp_1src" 0xffffffe0 0xdac123e0 (Outside [])
+ , Encoding "PACIA1716_HI_hints" 0xfffff23f 0xd503201f (Outside [])
+ , Encoding "PACIASP_HI_hints" 0xfffff23f 0xd503223f (Outside [])
+ , Encoding "PACIAZ_HI_hints" 0xfffff23f 0xd503221f (Outside [])
+ , Encoding "PACIB_64P_dp_1src" 0xfffffc00 0xdac10400 (Outside [(5, OpXSp)])
+ , Encoding "PACIZB_64Z_dp_1src" 0xffffffe0 0xdac127e0 (Outside [])
+ , Encoding "PACIB1716_HI_hints" 0xfffff23f 0xd503201f (Outside [])
+ , Encoding "PACIBSP_HI_hints" 0xfffff23f 0xd503223f (Outside [])
+ , Encoding "PACIBZ_HI_hints" 0xfffff23f 0xd503221f (Outside [])
+ , Encoding "PMUL_asimdsame_only" 0xbf20fc00 0x2e209c00 Covered
+ , Encoding "PMULL_asimddiff_L" 0xbf20fc00 0x0e20e000 Covered
+ , Encoding "PRFM_P_ldst_pos" 0xffc00000 0xf9800000 (Outside [])
+ , Encoding "PRFM_P_loadlit" 0xff000000 0xd8000000 (Outside [])
+ , Encoding "PRFM_P_ldst_regoff" 0xffe04c00 0xf8a04800 (Outside [])
+ , Encoding "PRFUM_P_ldst_unscaled" 0xffe00c00 0xf8800000 (Outside [])
+ , Encoding "PSB_HC_hints" 0xffffffff 0xd503223f Control
+ , Encoding "RADDHN_asimddiff_N" 0xbf20fc00 0x2e204000 Covered
+ , Encoding "RAX1_VVV2_cryptosha512_3" 0xffe0fc00 0xce608c00 Covered
+ , Encoding "RBIT_asimdmisc_R" 0xbffffc00 0x2e605800 Covered
+ , Encoding "RBIT_32_dp_1src" 0xfffffc00 0x5ac00000 Covered
+ , Encoding "RBIT_64_dp_1src" 0xfffffc00 0xdac00000 Covered
+ , Encoding "RCWCAS_C64_rcwcomswap" 0xffe0fc00 0x19200800 Covered
+ , Encoding "RCWCASA_C64_rcwcomswap" 0xffe0fc00 0x19a00800 Covered
+ , Encoding "RCWCASAL_C64_rcwcomswap" 0xffe0fc00 0x19e00800 Covered
+ , Encoding "RCWCASL_C64_rcwcomswap" 0xffe0fc00 0x19600800 Covered
+ , Encoding "RCWCASP_C64_rcwcomswappr" 0xffe0fc00 0x19200c00 Covered
+ , Encoding "RCWCASPA_C64_rcwcomswappr" 0xffe0fc00 0x19a00c00 Covered
+ , Encoding "RCWCASPAL_C64_rcwcomswappr" 0xffe0fc00 0x19e00c00 Covered
+ , Encoding "RCWCASPL_C64_rcwcomswappr" 0xffe0fc00 0x19600c00 Covered
+ , Encoding "RCWCLR_64_memop" 0xffe0fc00 0x38209000 Covered
+ , Encoding "RCWCLRA_64_memop" 0xffe0fc00 0x38a09000 Covered
+ , Encoding "RCWCLRAL_64_memop" 0xffe0fc00 0x38e09000 Covered
+ , Encoding "RCWCLRL_64_memop" 0xffe0fc00 0x38609000 Covered
+ , Encoding "RCWCLRP_128_memop_128" 0xffe0fc00 0x19209000 Covered
+ , Encoding "RCWCLRPA_128_memop_128" 0xffe0fc00 0x19a09000 Covered
+ , Encoding "RCWCLRPAL_128_memop_128" 0xffe0fc00 0x19e09000 Covered
+ , Encoding "RCWCLRPL_128_memop_128" 0xffe0fc00 0x19609000 Covered
+ , Encoding "RCWSCAS_C64_rcwcomswap" 0xffe0fc00 0x59200800 Covered
+ , Encoding "RCWSCASA_C64_rcwcomswap" 0xffe0fc00 0x59a00800 Covered
+ , Encoding "RCWSCASAL_C64_rcwcomswap" 0xffe0fc00 0x59e00800 Covered
+ , Encoding "RCWSCASL_C64_rcwcomswap" 0xffe0fc00 0x59600800 Covered
+ , Encoding "RCWSCASP_C64_rcwcomswappr" 0xffe0fc00 0x59200c00 Covered
+ , Encoding "RCWSCASPA_C64_rcwcomswappr" 0xffe0fc00 0x59a00c00 Covered
+ , Encoding "RCWSCASPAL_C64_rcwcomswappr" 0xffe0fc00 0x59e00c00 Covered
+ , Encoding "RCWSCASPL_C64_rcwcomswappr" 0xffe0fc00 0x59600c00 Covered
+ , Encoding "RCWSCLR_64_memop" 0xffe0fc00 0x78209000 Covered
+ , Encoding "RCWSCLRA_64_memop" 0xffe0fc00 0x78a09000 Covered
+ , Encoding "RCWSCLRAL_64_memop" 0xffe0fc00 0x78e09000 Covered
+ , Encoding "RCWSCLRL_64_memop" 0xffe0fc00 0x78609000 Covered
+ , Encoding "RCWSCLRP_128_memop_128" 0xffe0fc00 0x59209000 Covered
+ , Encoding "RCWSCLRPA_128_memop_128" 0xffe0fc00 0x59a09000 Covered
+ , Encoding "RCWSCLRPAL_128_memop_128" 0xffe0fc00 0x59e09000 Covered
+ , Encoding "RCWSCLRPL_128_memop_128" 0xffe0fc00 0x59609000 Covered
+ , Encoding "RCWSET_64_memop" 0xffe0fc00 0x3820b000 Covered
+ , Encoding "RCWSETA_64_memop" 0xffe0fc00 0x38a0b000 Covered
+ , Encoding "RCWSETAL_64_memop" 0xffe0fc00 0x38e0b000 Covered
+ , Encoding "RCWSETL_64_memop" 0xffe0fc00 0x3860b000 Covered
+ , Encoding "RCWSETP_128_memop_128" 0xffe0fc00 0x1920b000 Covered
+ , Encoding "RCWSETPA_128_memop_128" 0xffe0fc00 0x19a0b000 Covered
+ , Encoding "RCWSETPAL_128_memop_128" 0xffe0fc00 0x19e0b000 Covered
+ , Encoding "RCWSETPL_128_memop_128" 0xffe0fc00 0x1960b000 Covered
+ , Encoding "RCWSSET_64_memop" 0xffe0fc00 0x7820b000 Covered
+ , Encoding "RCWSSETA_64_memop" 0xffe0fc00 0x78a0b000 Covered
+ , Encoding "RCWSSETAL_64_memop" 0xffe0fc00 0x78e0b000 Covered
+ , Encoding "RCWSSETL_64_memop" 0xffe0fc00 0x7860b000 Covered
+ , Encoding "RCWSSETP_128_memop_128" 0xffe0fc00 0x5920b000 Covered
+ , Encoding "RCWSSETPA_128_memop_128" 0xffe0fc00 0x59a0b000 Covered
+ , Encoding "RCWSSETPAL_128_memop_128" 0xffe0fc00 0x59e0b000 Covered
+ , Encoding "RCWSSETPL_128_memop_128" 0xffe0fc00 0x5960b000 Covered
+ , Encoding "RCWSSWP_64_memop" 0xffe0fc00 0x7820a000 Covered
+ , Encoding "RCWSSWPA_64_memop" 0xffe0fc00 0x78a0a000 Covered
+ , Encoding "RCWSSWPAL_64_memop" 0xffe0fc00 0x78e0a000 Covered
+ , Encoding "RCWSSWPL_64_memop" 0xffe0fc00 0x7860a000 Covered
+ , Encoding "RCWSSWPP_128_memop_128" 0xffe0fc00 0x5920a000 Covered
+ , Encoding "RCWSSWPPA_128_memop_128" 0xffe0fc00 0x59a0a000 Covered
+ , Encoding "RCWSSWPPAL_128_memop_128" 0xffe0fc00 0x59e0a000 Covered
+ , Encoding "RCWSSWPPL_128_memop_128" 0xffe0fc00 0x5960a000 Covered
+ , Encoding "RCWSWP_64_memop" 0xffe0fc00 0x3820a000 Covered
+ , Encoding "RCWSWPA_64_memop" 0xffe0fc00 0x38a0a000 Covered
+ , Encoding "RCWSWPAL_64_memop" 0xffe0fc00 0x38e0a000 Covered
+ , Encoding "RCWSWPL_64_memop" 0xffe0fc00 0x3860a000 Covered
+ , Encoding "RCWSWPP_128_memop_128" 0xffe0fc00 0x1920a000 Covered
+ , Encoding "RCWSWPPA_128_memop_128" 0xffe0fc00 0x19a0a000 Covered
+ , Encoding "RCWSWPPAL_128_memop_128" 0xffe0fc00 0x19e0a000 Covered
+ , Encoding "RCWSWPPL_128_memop_128" 0xffe0fc00 0x1960a000 Covered
+ , Encoding "RET_64R_branch_reg" 0xfffffc1f 0xd65f0000 Control
+ , Encoding "RETAA_64E_branch_reg" 0xffffffff 0xd65f0bff Control
+ , Encoding "RETAB_64E_branch_reg" 0xffffffff 0xd65f0fff Control
+ , Encoding "REV_32_dp_1src" 0xfffff400 0x5ac00000 Covered
+ , Encoding "REV_64_dp_1src" 0xfffff400 0xdac00400 Covered
+ , Encoding "REV16_asimdmisc_R" 0xbf3ffc00 0x0e201800 Covered
+ , Encoding "REV16_32_dp_1src" 0xfffffc00 0x5ac00400 Covered
+ , Encoding "REV16_64_dp_1src" 0xfffffc00 0xdac00400 Covered
+ , Encoding "REV32_asimdmisc_R" 0xbf3ffc00 0x2e200800 Covered
+ , Encoding "REV32_64_dp_1src" 0xfffffc00 0xdac00800 Covered
+ , Encoding "REV64_asimdmisc_R" 0xbf3ffc00 0x0e200800 Covered
+ , Encoding "RMIF_only_rmif" 0xffe07c10 0xba000400 Covered
+ , Encoding "RORV_32_dp_2src" 0xffe0fc00 0x1ac02c00 Covered
+ , Encoding "RORV_64_dp_2src" 0xffe0fc00 0x9ac02c00 Covered
+ , Encoding "RPRFM_R_ldst_regoff" 0xffe04c18 0xf8a04818 (Outside [(16, OpX)])
+ , Encoding "RSHRN_asimdshf_N" 0xbf80fc00 0x0f008c00 Covered
+ , Encoding "RSUBHN_asimddiff_N" 0xbf20fc00 0x2e206000 Covered
+ , Encoding "SABA_asimdsame_only" 0xbf20fc00 0x0e207c00 Covered
+ , Encoding "SABAL_asimddiff_L" 0xbf20fc00 0x0e205000 Covered
+ , Encoding "SABD_asimdsame_only" 0xbf20fc00 0x0e207400 Covered
+ , Encoding "SABDL_asimddiff_L" 0xbf20fc00 0x0e207000 Covered
+ , Encoding "SADALP_asimdmisc_P" 0xbf3ffc00 0x0e206800 Covered
+ , Encoding "SADDL_asimddiff_L" 0xbf20fc00 0x0e200000 Covered
+ , Encoding "SADDLP_asimdmisc_P" 0xbf3ffc00 0x0e202800 Covered
+ , Encoding "SADDLV_asimdall_only" 0xbf3ffc00 0x0e303800 Covered
+ , Encoding "SADDW_asimddiff_W" 0xbf20fc00 0x0e201000 Covered
+ , Encoding "SB_only_barriers" 0xfffff0ff 0xd50330ff Control
+ , Encoding "SBC_32_addsub_carry" 0xffe0fc00 0x5a000000 Covered
+ , Encoding "SBC_64_addsub_carry" 0xffe0fc00 0xda000000 Covered
+ , Encoding "SBCS_32_addsub_carry" 0xffe0fc00 0x7a000000 Covered
+ , Encoding "SBCS_64_addsub_carry" 0xffe0fc00 0xfa000000 Covered
+ , Encoding "SBFM_32M_bitfield" 0xffc00000 0x13000000 Covered
+ , Encoding "SBFM_64M_bitfield" 0xffc00000 0x93400000 Covered
+ , Encoding "SCVTF_asisdshf_C" 0xff80fc00 0x5f00e400 (Outside [])
+ , Encoding "SCVTF_asimdshf_C" 0xbf80fc00 0x0f00e400 (Outside [(5, OpV)])
+ , Encoding "SCVTF_asisdmiscfp16_R" 0xfffffc00 0x5e79d800 (Outside [(5, OpH)])
+ , Encoding "SCVTF_asisdmisc_R" 0xffbffc00 0x5e21d800 (Outside [])
+ , Encoding "SCVTF_asimdmiscfp16_R" 0xbffffc00 0x0e79d800 (Outside [(5, OpV)])
+ , Encoding "SCVTF_asimdmisc_R" 0xbfbffc00 0x0e21d800 (Outside [(5, OpV)])
+ , Encoding "SCVTF_H32_float2fix" 0xffff0000 0x1ec20000 (Outside [(5, OpW)])
+ , Encoding "SCVTF_S32_float2fix" 0xffff0000 0x1e020000 (Outside [(5, OpW)])
+ , Encoding "SCVTF_D32_float2fix" 0xffff0000 0x1e420000 (Outside [(5, OpW)])
+ , Encoding "SCVTF_H64_float2fix" 0xffff0000 0x9ec20000 (Outside [(5, OpX)])
+ , Encoding "SCVTF_S64_float2fix" 0xffff0000 0x9e020000 (Outside [(5, OpX)])
+ , Encoding "SCVTF_D64_float2fix" 0xffff0000 0x9e420000 (Outside [(5, OpX)])
+ , Encoding "SCVTF_H32_float2int" 0xfffffc00 0x1ee20000 (Outside [(5, OpW)])
+ , Encoding "SCVTF_S32_float2int" 0xfffffc00 0x1e220000 (Outside [(5, OpW)])
+ , Encoding "SCVTF_D32_float2int" 0xfffffc00 0x1e620000 (Outside [(5, OpW)])
+ , Encoding "SCVTF_H64_float2int" 0xfffffc00 0x9ee20000 (Outside [(5, OpX)])
+ , Encoding "SCVTF_S64_float2int" 0xfffffc00 0x9e220000 (Outside [(5, OpX)])
+ , Encoding "SCVTF_D64_float2int" 0xfffffc00 0x9e620000 (Outside [(5, OpX)])
+ , Encoding "SDIV_32_dp_2src" 0xffe0fc00 0x1ac00c00
+ (Outside [(5, OpW), (16, OpW)])
+ , Encoding "SDIV_64_dp_2src" 0xffe0fc00 0x9ac00c00
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SDOT_asimdelem_D" 0xbf00f400 0x0f00e000
+ (Outside [(0, OpV), (5, OpV)])
+ , Encoding "SDOT_asimdsame2_D" 0xbf20fc00 0x0e009400
+ (Outside [(0, OpV), (5, OpV), (16, OpV)])
+ , Encoding "SETF8_only_setf" 0xfffffc1f 0x3a00080d Covered
+ , Encoding "SETF16_only_setf" 0xfffffc1f 0x3a00480d Covered
+ , Encoding "SETGE_SET_memcms" 0x3fe0cc00 0x1dc08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGM_SET_memcms" 0x3fe0cc00 0x1dc04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGP_SET_memcms" 0x3fe0cc00 0x1dc00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGEN_SET_memcms" 0x3fe0cc00 0x1dc08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGMN_SET_memcms" 0x3fe0cc00 0x1dc04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGPN_SET_memcms" 0x3fe0cc00 0x1dc00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGET_SET_memcms" 0x3fe0cc00 0x1dc08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGMT_SET_memcms" 0x3fe0cc00 0x1dc04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGPT_SET_memcms" 0x3fe0cc00 0x1dc00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGETN_SET_memcms" 0x3fe0cc00 0x1dc08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGMTN_SET_memcms" 0x3fe0cc00 0x1dc04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETGPTN_SET_memcms" 0x3fe0cc00 0x1dc00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETE_SET_memcms" 0x3fe0cc00 0x19c08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETM_SET_memcms" 0x3fe0cc00 0x19c04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETP_SET_memcms" 0x3fe0cc00 0x19c00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETEN_SET_memcms" 0x3fe0cc00 0x19c08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETMN_SET_memcms" 0x3fe0cc00 0x19c04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETPN_SET_memcms" 0x3fe0cc00 0x19c00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETET_SET_memcms" 0x3fe0cc00 0x19c08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETMT_SET_memcms" 0x3fe0cc00 0x19c04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETPT_SET_memcms" 0x3fe0cc00 0x19c00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETETN_SET_memcms" 0x3fe0cc00 0x19c08400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETMTN_SET_memcms" 0x3fe0cc00 0x19c04400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SETPTN_SET_memcms" 0x3fe0cc00 0x19c00400
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "SEV_HI_hints" 0xffffffff 0xd503209f Control
+ , Encoding "SEVL_HI_hints" 0xffffffff 0xd50320bf Control
+ , Encoding "SHA1C_QSV_cryptosha3" 0xffe0fc00 0x5e000000 Covered
+ , Encoding "SHA1H_SS_cryptosha2" 0xfffffc00 0x5e280800 Covered
+ , Encoding "SHA1M_QSV_cryptosha3" 0xffe0fc00 0x5e002000 Covered
+ , Encoding "SHA1P_QSV_cryptosha3" 0xffe0fc00 0x5e001000 Covered
+ , Encoding "SHA1SU0_VVV_cryptosha3" 0xffe0fc00 0x5e003000 Covered
+ , Encoding "SHA1SU1_VV_cryptosha2" 0xfffffc00 0x5e281800 Covered
+ , Encoding "SHA256H2_QQV_cryptosha3" 0xffe0fc00 0x5e005000 Covered
+ , Encoding "SHA256H_QQV_cryptosha3" 0xffe0fc00 0x5e004000 Covered
+ , Encoding "SHA256SU0_VV_cryptosha2" 0xfffffc00 0x5e282800 Covered
+ , Encoding "SHA256SU1_VVV_cryptosha3" 0xffe0fc00 0x5e006000 Covered
+ , Encoding "SHA512H2_QQV_cryptosha512_3" 0xffe0fc00 0xce608400 Covered
+ , Encoding "SHA512H_QQV_cryptosha512_3" 0xffe0fc00 0xce608000 Covered
+ , Encoding "SHA512SU0_VV2_cryptosha512_2" 0xfffffc00 0xcec08000 Covered
+ , Encoding "SHA512SU1_VVV2_cryptosha512_3" 0xffe0fc00 0xce608800 Covered
+ , Encoding "SHADD_asimdsame_only" 0xbf20fc00 0x0e200400 Covered
+ , Encoding "SHL_asisdshf_R" 0xff80fc00 0x5f005400 Covered
+ , Encoding "SHL_asimdshf_R" 0xbf80fc00 0x0f005400 Covered
+ , Encoding "SHLL_asimdmisc_S" 0xbf3ffc00 0x2e213800 Covered
+ , Encoding "SHRN_asimdshf_N" 0xbf80fc00 0x0f008400 Covered
+ , Encoding "SHSUB_asimdsame_only" 0xbf20fc00 0x0e202400 Covered
+ , Encoding "SLI_asisdshf_R" 0xff80fc00 0x7f005400 Covered
+ , Encoding "SLI_asimdshf_R" 0xbf80fc00 0x2f005400 Covered
+ , Encoding "SM3PARTW1_VVV4_cryptosha512_3" 0xffe0fc00 0xce60c000 Covered
+ , Encoding "SM3PARTW2_VVV4_cryptosha512_3" 0xffe0fc00 0xce60c400 Covered
+ , Encoding "SM3SS1_VVV4_crypto4" 0xffe08000 0xce400000 Covered
+ , Encoding "SM3TT1A_VVV4_crypto3_imm2" 0xffe0cc00 0xce408000 Covered
+ , Encoding "SM3TT1B_VVV4_crypto3_imm2" 0xffe0cc00 0xce408400 Covered
+ , Encoding "SM3TT2A_VVV4_crypto3_imm2" 0xffe0cc00 0xce408800 Covered
+ , Encoding "SM3TT2B_VVV_crypto3_imm2" 0xffe0cc00 0xce408c00 Covered
+ , Encoding "SM4E_VV4_cryptosha512_2" 0xfffffc00 0xcec08400 Covered
+ , Encoding "SM4EKEY_VVV4_cryptosha512_3" 0xffe0fc00 0xce60c800 Covered
+ , Encoding "SMADDL_64WA_dp_3src" 0xffe08000 0x9b200000 Covered
+ , Encoding "SMAX_asimdsame_only" 0xbf20fc00 0x0e206400 Covered
+ , Encoding "SMAX_32_minmax_imm" 0xfffc0000 0x11c00000 Covered
+ , Encoding "SMAX_64_minmax_imm" 0xfffc0000 0x91c00000 Covered
+ , Encoding "SMAX_32_dp_2src" 0xffe0fc00 0x1ac06000 Covered
+ , Encoding "SMAX_64_dp_2src" 0xffe0fc00 0x9ac06000 Covered
+ , Encoding "SMAXP_asimdsame_only" 0xbf20fc00 0x0e20a400 Covered
+ , Encoding "SMAXV_asimdall_only" 0xbf3ffc00 0x0e30a800 Covered
+ , Encoding "SMC_EX_exception" 0xffe0001f 0xd4000003 Control
+ , Encoding "SMIN_asimdsame_only" 0xbf20fc00 0x0e206c00 Covered
+ , Encoding "SMIN_32_minmax_imm" 0xfffc0000 0x11c80000 Covered
+ , Encoding "SMIN_64_minmax_imm" 0xfffc0000 0x91c80000 Covered
+ , Encoding "SMIN_32_dp_2src" 0xffe0fc00 0x1ac06800 Covered
+ , Encoding "SMIN_64_dp_2src" 0xffe0fc00 0x9ac06800 Covered
+ , Encoding "SMINP_asimdsame_only" 0xbf20fc00 0x0e20ac00 Covered
+ , Encoding "SMINV_asimdall_only" 0xbf3ffc00 0x0e31a800 Covered
+ , Encoding "SMLAL_asimdelem_L" 0xbf00f400 0x0f002000 Covered
+ , Encoding "SMLAL_asimddiff_L" 0xbf20fc00 0x0e208000 Covered
+ , Encoding "SMLSL_asimdelem_L" 0xbf00f400 0x0f006000 Covered
+ , Encoding "SMLSL_asimddiff_L" 0xbf20fc00 0x0e20a000 Covered
+ , Encoding "SMMLA_asimdsame2_G" 0xffe0fc00 0x4e80a400
+ (Outside [(0, OpV), (5, OpV), (16, OpV)])
+ , Encoding "SMOV_asimdins_W_w" 0xffe0fc00 0x0e002c00 Covered
+ , Encoding "SMOV_asimdins_X_x" 0xffe0fc00 0x4e002c00 Covered
+ , Encoding "SMSUBL_64WA_dp_3src" 0xffe08000 0x9b208000 Covered
+ , Encoding "SMULH_64_dp_3src" 0xffe08000 0x9b400000 Covered
+ , Encoding "SMULL_asimdelem_L" 0xbf00f400 0x0f00a000 Covered
+ , Encoding "SMULL_asimddiff_L" 0xbf20fc00 0x0e20c000 Covered
+ , Encoding "SQABS_asisdmisc_R" 0xff3ffc00 0x5e207800 (Outside [])
+ , Encoding "SQABS_asimdmisc_R" 0xbf3ffc00 0x0e207800 (Outside [(5, OpV)])
+ , Encoding "SQADD_asisdsame_only" 0xff20fc00 0x5e200c00 (Outside [])
+ , Encoding "SQADD_asimdsame_only" 0xbf20fc00 0x0e200c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQDMLAL_asisdelem_L" 0xff00f400 0x5f003000 (Outside [])
+ , Encoding "SQDMLAL_asimdelem_L" 0xbf00f400 0x0f003000 (Outside [(5, OpV)])
+ , Encoding "SQDMLAL_asisddiff_only" 0xff20fc00 0x5e209000 (Outside [])
+ , Encoding "SQDMLAL_asimddiff_L" 0xbf20fc00 0x0e209000
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQDMLSL_asisdelem_L" 0xff00f400 0x5f007000 (Outside [])
+ , Encoding "SQDMLSL_asimdelem_L" 0xbf00f400 0x0f007000 (Outside [(5, OpV)])
+ , Encoding "SQDMLSL_asisddiff_only" 0xff20fc00 0x5e20b000 (Outside [])
+ , Encoding "SQDMLSL_asimddiff_L" 0xbf20fc00 0x0e20b000
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQDMULH_asisdelem_R" 0xff00f400 0x5f00c000 Covered
+ , Encoding "SQDMULH_asimdelem_R" 0xbf00f400 0x0f00c000 Covered
+ , Encoding "SQDMULH_asisdsame_only" 0xff20fc00 0x5e20b400 Covered
+ , Encoding "SQDMULH_asimdsame_only" 0xbf20fc00 0x0e20b400 Covered
+ , Encoding "SQDMULL_asisdelem_L" 0xff00f400 0x5f00b000 (Outside [])
+ , Encoding "SQDMULL_asimdelem_L" 0xbf00f400 0x0f00b000 (Outside [(5, OpV)])
+ , Encoding "SQDMULL_asisddiff_only" 0xff20fc00 0x5e20d000 (Outside [])
+ , Encoding "SQDMULL_asimddiff_L" 0xbf20fc00 0x0e20d000
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQNEG_asisdmisc_R" 0xff3ffc00 0x7e207800 (Outside [])
+ , Encoding "SQNEG_asimdmisc_R" 0xbf3ffc00 0x2e207800 (Outside [(5, OpV)])
+ , Encoding "SQRDMLAH_asisdelem_R" 0xff00f400 0x7f00d000 Covered
+ , Encoding "SQRDMLAH_asimdelem_R" 0xbf00f400 0x2f00d000 Covered
+ , Encoding "SQRDMLAH_asisdsame2_only" 0xff20fc00 0x7e008400 Covered
+ , Encoding "SQRDMLAH_asimdsame2_only" 0xbf20fc00 0x2e008400 Covered
+ , Encoding "SQRDMLSH_asisdelem_R" 0xff00f400 0x7f00f000 (Outside [])
+ , Encoding "SQRDMLSH_asimdelem_R" 0xbf00f400 0x2f00f000 (Outside [(5, OpV)])
+ , Encoding "SQRDMLSH_asisdsame2_only" 0xff20fc00 0x7e008c00 (Outside [])
+ , Encoding "SQRDMLSH_asimdsame2_only" 0xbf20fc00 0x2e008c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQRDMULH_asisdelem_R" 0xff00f400 0x5f00d000 Covered
+ , Encoding "SQRDMULH_asimdelem_R" 0xbf00f400 0x0f00d000 Covered
+ , Encoding "SQRDMULH_asisdsame_only" 0xff20fc00 0x7e20b400 Covered
+ , Encoding "SQRDMULH_asimdsame_only" 0xbf20fc00 0x2e20b400 Covered
+ , Encoding "SQRSHL_asisdsame_only" 0xff20fc00 0x5e205c00 (Outside [])
+ , Encoding "SQRSHL_asimdsame_only" 0xbf20fc00 0x0e205c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQRSHRN_asisdshf_N" 0xff80fc00 0x5f009c00 (Outside [])
+ , Encoding "SQRSHRN_asimdshf_N" 0xbf80fc00 0x0f009c00 (Outside [(5, OpV)])
+ , Encoding "SQRSHRUN_asisdshf_N" 0xff80fc00 0x7f008c00 (Outside [])
+ , Encoding "SQRSHRUN_asimdshf_N" 0xbf80fc00 0x2f008c00 (Outside [(5, OpV)])
+ , Encoding "SQSHL_asisdshf_R" 0xff80fc00 0x5f007400 (Outside [])
+ , Encoding "SQSHL_asimdshf_R" 0xbf80fc00 0x0f007400 (Outside [(5, OpV)])
+ , Encoding "SQSHL_asisdsame_only" 0xff20fc00 0x5e204c00 (Outside [])
+ , Encoding "SQSHL_asimdsame_only" 0xbf20fc00 0x0e204c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQSHLU_asisdshf_R" 0xff80fc00 0x7f006400 (Outside [])
+ , Encoding "SQSHLU_asimdshf_R" 0xbf80fc00 0x2f006400 (Outside [(5, OpV)])
+ , Encoding "SQSHRN_asisdshf_N" 0xff80fc00 0x5f009400 (Outside [])
+ , Encoding "SQSHRN_asimdshf_N" 0xbf80fc00 0x0f009400 (Outside [(5, OpV)])
+ , Encoding "SQSHRUN_asisdshf_N" 0xff80fc00 0x7f008400 (Outside [])
+ , Encoding "SQSHRUN_asimdshf_N" 0xbf80fc00 0x2f008400 (Outside [(5, OpV)])
+ , Encoding "SQSUB_asisdsame_only" 0xff20fc00 0x5e202c00 (Outside [])
+ , Encoding "SQSUB_asimdsame_only" 0xbf20fc00 0x0e202c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SQXTN_asisdmisc_N" 0xff3ffc00 0x5e214800 (Outside [])
+ , Encoding "SQXTN_asimdmisc_N" 0xbf3ffc00 0x0e214800 (Outside [(5, OpV)])
+ , Encoding "SQXTUN_asisdmisc_N" 0xff3ffc00 0x7e212800 (Outside [])
+ , Encoding "SQXTUN_asimdmisc_N" 0xbf3ffc00 0x2e212800 (Outside [(5, OpV)])
+ , Encoding "SRHADD_asimdsame_only" 0xbf20fc00 0x0e201400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SRI_asisdshf_R" 0xff80fc00 0x7f004400 Covered
+ , Encoding "SRI_asimdshf_R" 0xbf80fc00 0x2f004400 Covered
+ , Encoding "SRSHL_asisdsame_only" 0xff20fc00 0x5e205400 (Outside [])
+ , Encoding "SRSHL_asimdsame_only" 0xbf20fc00 0x0e205400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "SRSHR_asisdshf_R" 0xff80fc00 0x5f002400 (Outside [])
+ , Encoding "SRSHR_asimdshf_R" 0xbf80fc00 0x0f002400 (Outside [(5, OpV)])
+ , Encoding "SRSRA_asisdshf_R" 0xff80fc00 0x5f003400 (Outside [])
+ , Encoding "SRSRA_asimdshf_R" 0xbf80fc00 0x0f003400 (Outside [(5, OpV)])
+ , Encoding "SSHL_asisdsame_only" 0xff20fc00 0x5e204400 Covered
+ , Encoding "SSHL_asimdsame_only" 0xbf20fc00 0x0e204400 Covered
+ , Encoding "SSHLL_asimdshf_L" 0xbf80fc00 0x0f00a400 Covered
+ , Encoding "SSHR_asisdshf_R" 0xff80fc00 0x5f000400 Covered
+ , Encoding "SSHR_asimdshf_R" 0xbf80fc00 0x0f000400 Covered
+ , Encoding "SSRA_asisdshf_R" 0xff80fc00 0x5f001400 Covered
+ , Encoding "SSRA_asimdshf_R" 0xbf80fc00 0x0f001400 Covered
+ , Encoding "SSUBL_asimddiff_L" 0xbf20fc00 0x0e202000 Covered
+ , Encoding "SSUBW_asimddiff_W" 0xbf20fc00 0x0e203000 Covered
+ , Encoding "ST1_asisdlse_R1_1v" 0xbfffd000 0x0c005000 Covered
+ , Encoding "ST1_asisdlse_R2_2v" 0xbfffd000 0x0c008000 Covered
+ , Encoding "ST1_asisdlse_R3_3v" 0xbfffd000 0x0c004000 Covered
+ , Encoding "ST1_asisdlse_R4_4v" 0xbfffd000 0x0c000000 Covered
+ , Encoding "ST1_asisdlsep_I1_i1" 0xbfffd000 0x0c9f5000 Covered
+ , Encoding "ST1_asisdlsep_R1_r1" 0xbfe0d000 0x0c805000 Covered
+ , Encoding "ST1_asisdlsep_I2_i2" 0xbfffd000 0x0c9f8000 Covered
+ , Encoding "ST1_asisdlsep_R2_r2" 0xbfe0d000 0x0c808000 Covered
+ , Encoding "ST1_asisdlsep_I3_i3" 0xbfffd000 0x0c9f4000 Covered
+ , Encoding "ST1_asisdlsep_R3_r3" 0xbfe0d000 0x0c804000 Covered
+ , Encoding "ST1_asisdlsep_I4_i4" 0xbfffd000 0x0c9f0000 Covered
+ , Encoding "ST1_asisdlsep_R4_r4" 0xbfe0d000 0x0c800000 Covered
+ , Encoding "ST1_asisdlso_B1_1b" 0xbfffc000 0x0d000000 Covered
+ , Encoding "ST1_asisdlso_H1_1h" 0xbfffc400 0x0d004000 Covered
+ , Encoding "ST1_asisdlso_S1_1s" 0xbfffcc00 0x0d008000 Covered
+ , Encoding "ST1_asisdlso_D1_1d" 0xbfffdc00 0x0d008400 Covered
+ , Encoding "ST1_asisdlsop_B1_i1b" 0xbfffc000 0x0d9f0000 Covered
+ , Encoding "ST1_asisdlsop_BX1_r1b" 0xbfe0c000 0x0d800000 Covered
+ , Encoding "ST1_asisdlsop_H1_i1h" 0xbfffc400 0x0d9f4000 Covered
+ , Encoding "ST1_asisdlsop_HX1_r1h" 0xbfe0c400 0x0d804000 Covered
+ , Encoding "ST1_asisdlsop_S1_i1s" 0xbfffcc00 0x0d9f8000 Covered
+ , Encoding "ST1_asisdlsop_SX1_r1s" 0xbfe0cc00 0x0d808000 Covered
+ , Encoding "ST1_asisdlsop_D1_i1d" 0xbfffdc00 0x0d9f8400 Covered
+ , Encoding "ST1_asisdlsop_DX1_r1d" 0xbfe0dc00 0x0d808400 Covered
+ , Encoding "ST2_asisdlse_R2" 0xbffff000 0x0c008000 Covered
+ , Encoding "ST2_asisdlsep_I2_i" 0xbffff000 0x0c9f8000 Covered
+ , Encoding "ST2_asisdlsep_R2_r" 0xbfe0f000 0x0c808000 Covered
+ , Encoding "ST2_asisdlso_B2_2b" 0xbfffc000 0x0d200000 Covered
+ , Encoding "ST2_asisdlso_H2_2h" 0xbfffc400 0x0d204000 Covered
+ , Encoding "ST2_asisdlso_S2_2s" 0xbfffcc00 0x0d208000 Covered
+ , Encoding "ST2_asisdlso_D2_2d" 0xbfffdc00 0x0d208400 Covered
+ , Encoding "ST2_asisdlsop_B2_i2b" 0xbfffc000 0x0dbf0000 Covered
+ , Encoding "ST2_asisdlsop_BX2_r2b" 0xbfe0c000 0x0da00000 Covered
+ , Encoding "ST2_asisdlsop_H2_i2h" 0xbfffc400 0x0dbf4000 Covered
+ , Encoding "ST2_asisdlsop_HX2_r2h" 0xbfe0c400 0x0da04000 Covered
+ , Encoding "ST2_asisdlsop_S2_i2s" 0xbfffcc00 0x0dbf8000 Covered
+ , Encoding "ST2_asisdlsop_SX2_r2s" 0xbfe0cc00 0x0da08000 Covered
+ , Encoding "ST2_asisdlsop_D2_i2d" 0xbfffdc00 0x0dbf8400 Covered
+ , Encoding "ST2_asisdlsop_DX2_r2d" 0xbfe0dc00 0x0da08400 Covered
+ , Encoding "ST2G_64Spost_ldsttags" 0xffe00c00 0xd9a00400
+ (Outside [(0, OpXSp)])
+ , Encoding "ST2G_64Spre_ldsttags" 0xffe00c00 0xd9a00c00
+ (Outside [(0, OpXSp)])
+ , Encoding "ST2G_64Soffset_ldsttags" 0xffe00c00 0xd9a00800
+ (Outside [(0, OpXSp)])
+ , Encoding "ST3_asisdlse_R3" 0xbffff000 0x0c004000 Covered
+ , Encoding "ST3_asisdlsep_I3_i" 0xbffff000 0x0c9f4000 Covered
+ , Encoding "ST3_asisdlsep_R3_r" 0xbfe0f000 0x0c804000 Covered
+ , Encoding "ST3_asisdlso_B3_3b" 0xbfffc000 0x0d000000 Covered
+ , Encoding "ST3_asisdlso_H3_3h" 0xbfffc400 0x0d004000 Covered
+ , Encoding "ST3_asisdlso_S3_3s" 0xbfffcc00 0x0d008000 Covered
+ , Encoding "ST3_asisdlso_D3_3d" 0xbfffdc00 0x0d008400 Covered
+ , Encoding "ST3_asisdlsop_B3_i3b" 0xbfffc000 0x0d9f0000 Covered
+ , Encoding "ST3_asisdlsop_BX3_r3b" 0xbfe0c000 0x0d800000 Covered
+ , Encoding "ST3_asisdlsop_H3_i3h" 0xbfffc400 0x0d9f4000 Covered
+ , Encoding "ST3_asisdlsop_HX3_r3h" 0xbfe0c400 0x0d804000 Covered
+ , Encoding "ST3_asisdlsop_S3_i3s" 0xbfffcc00 0x0d9f8000 Covered
+ , Encoding "ST3_asisdlsop_SX3_r3s" 0xbfe0cc00 0x0d808000 Covered
+ , Encoding "ST3_asisdlsop_D3_i3d" 0xbfffdc00 0x0d9f8400 Covered
+ , Encoding "ST3_asisdlsop_DX3_r3d" 0xbfe0dc00 0x0d808400 Covered
+ , Encoding "ST4_asisdlse_R4" 0xbffff000 0x0c000000 Covered
+ , Encoding "ST4_asisdlsep_I4_i" 0xbffff000 0x0c9f0000 Covered
+ , Encoding "ST4_asisdlsep_R4_r" 0xbfe0f000 0x0c800000 Covered
+ , Encoding "ST4_asisdlso_B4_4b" 0xbfffc000 0x0d200000 Covered
+ , Encoding "ST4_asisdlso_H4_4h" 0xbfffc400 0x0d204000 Covered
+ , Encoding "ST4_asisdlso_S4_4s" 0xbfffcc00 0x0d208000 Covered
+ , Encoding "ST4_asisdlso_D4_4d" 0xbfffdc00 0x0d208400 Covered
+ , Encoding "ST4_asisdlsop_B4_i4b" 0xbfffc000 0x0dbf0000 Covered
+ , Encoding "ST4_asisdlsop_BX4_r4b" 0xbfe0c000 0x0da00000 Covered
+ , Encoding "ST4_asisdlsop_H4_i4h" 0xbfffc400 0x0dbf4000 Covered
+ , Encoding "ST4_asisdlsop_HX4_r4h" 0xbfe0c400 0x0da04000 Covered
+ , Encoding "ST4_asisdlsop_S4_i4s" 0xbfffcc00 0x0dbf8000 Covered
+ , Encoding "ST4_asisdlsop_SX4_r4s" 0xbfe0cc00 0x0da08000 Covered
+ , Encoding "ST4_asisdlsop_D4_i4d" 0xbfffdc00 0x0dbf8400 Covered
+ , Encoding "ST4_asisdlsop_DX4_r4d" 0xbfe0dc00 0x0da08400 Covered
+ , Encoding "ST64B_64L_memop" 0xfffffc00 0xf83f9000 (Outside [(0, OpX)])
+ , Encoding "ST64BV_64_memop" 0xffe0fc00 0xf820b000
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "ST64BV0_64_memop" 0xffe0fc00 0xf820a000
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "STG_64Spost_ldsttags" 0xffe00c00 0xd9200400
+ (Outside [(0, OpXSp)])
+ , Encoding "STG_64Spre_ldsttags" 0xffe00c00 0xd9200c00 (Outside [(0, OpXSp)])
+ , Encoding "STG_64Soffset_ldsttags" 0xffe00c00 0xd9200800
+ (Outside [(0, OpXSp)])
+ , Encoding "STGM_64bulk_ldsttags" 0xfffffc00 0xd9a00000 (Outside [(0, OpX)])
+ , Encoding "STGP_64_ldstpair_post" 0xffc00000 0x68800000
+ (Outside [(0, OpX), (10, OpX)])
+ , Encoding "STGP_64_ldstpair_pre" 0xffc00000 0x69800000
+ (Outside [(0, OpX), (10, OpX)])
+ , Encoding "STGP_64_ldstpair_off" 0xffc00000 0x69000000
+ (Outside [(0, OpX), (10, OpX)])
+ , Encoding "STILP_32S_ldiappstilp" 0x7fe01c00 0x19001800 Covered
+ , Encoding "STILP_32SE_ldiappstilp" 0x7fe01c00 0x19000800 Covered
+ , Encoding "STILP_64S_ldiappstilp" 0x7fe01c00 0x59001800 Covered
+ , Encoding "STILP_64SS_ldiappstilp" 0x7fe01c00 0x59000800 Covered
+ , Encoding "STL1_asisdlso_D1" 0xbffffc00 0x0d018400 Covered
+ , Encoding "STLLR_SL32_ldstord" 0x7fe08000 0x08800000 Covered
+ , Encoding "STLLR_SL64_ldstord" 0x7fe08000 0x48800000 Covered
+ , Encoding "STLLRB_SL32_ldstord" 0xffe08000 0x08800000 Covered
+ , Encoding "STLLRH_SL32_ldstord" 0xffe08000 0x48800000 Covered
+ , Encoding "STLR_SL32_ldstord" 0x7fe08000 0x08808000 Covered
+ , Encoding "STLR_SL64_ldstord" 0x7fe08000 0x48808000 Covered
+ , Encoding "STLR_32S_ldapstl_writeback" 0x7ffffc00 0x19800800 Covered
+ , Encoding "STLR_64S_ldapstl_writeback" 0x7ffffc00 0x59800800 Covered
+ , Encoding "STLRB_SL32_ldstord" 0xffe08000 0x08808000 Covered
+ , Encoding "STLRH_SL32_ldstord" 0xffe08000 0x48808000 Covered
+ , Encoding "STLUR_B_ldapstl_simd" 0xffa00c00 0x1d000800 Covered
+ , Encoding "STLUR_H_ldapstl_simd" 0xffa00c00 0x5d000800 Covered
+ , Encoding "STLUR_S_ldapstl_simd" 0xffa00c00 0x9d000800 Covered
+ , Encoding "STLUR_D_ldapstl_simd" 0xffa00c00 0xdd000800 Covered
+ , Encoding "STLUR_Q_ldapstl_simd" 0xffa00c00 0x1d800800 Covered
+ , Encoding "STLUR_32_ldapstl_unscaled" 0x7fe00c00 0x19000000 Covered
+ , Encoding "STLUR_64_ldapstl_unscaled" 0x7fe00c00 0x59000000 Covered
+ , Encoding "STLURB_32_ldapstl_unscaled" 0xffe00c00 0x19000000 Covered
+ , Encoding "STLURH_32_ldapstl_unscaled" 0xffe00c00 0x59000000 Covered
+ , Encoding "STLXP_SP32_ldstexclp" 0xffe08000 0x88208000 Covered
+ , Encoding "STLXP_SP64_ldstexclp" 0xffe08000 0xc8208000 Covered
+ , Encoding "STLXR_SR32_ldstexclr" 0x7fe08000 0x08008000 Covered
+ , Encoding "STLXR_SR64_ldstexclr" 0x7fe08000 0x48008000 Covered
+ , Encoding "STLXRB_SR32_ldstexclr" 0xffe08000 0x08008000 Covered
+ , Encoding "STLXRH_SR32_ldstexclr" 0xffe08000 0x48008000 Covered
+ , Encoding "STNP_S_ldstnapair_offs" 0xffc00000 0x2c000000 Covered
+ , Encoding "STNP_D_ldstnapair_offs" 0xffc00000 0x6c000000 Covered
+ , Encoding "STNP_Q_ldstnapair_offs" 0xffc00000 0xac000000 Covered
+ , Encoding "STNP_32_ldstnapair_offs" 0xbfc00000 0x28000000 Covered
+ , Encoding "STNP_64_ldstnapair_offs" 0xbfc00000 0xa8000000 Covered
+ , Encoding "STP_S_ldstpair_post" 0xffc00000 0x2c800000 Covered
+ , Encoding "STP_D_ldstpair_post" 0xffc00000 0x6c800000 Covered
+ , Encoding "STP_Q_ldstpair_post" 0xffc00000 0xac800000 Covered
+ , Encoding "STP_S_ldstpair_pre" 0xffc00000 0x2d800000 Covered
+ , Encoding "STP_D_ldstpair_pre" 0xffc00000 0x6d800000 Covered
+ , Encoding "STP_Q_ldstpair_pre" 0xffc00000 0xad800000 Covered
+ , Encoding "STP_S_ldstpair_off" 0xffc00000 0x2d000000 Covered
+ , Encoding "STP_D_ldstpair_off" 0xffc00000 0x6d000000 Covered
+ , Encoding "STP_Q_ldstpair_off" 0xffc00000 0xad000000 Covered
+ , Encoding "STP_32_ldstpair_post" 0xbfc00000 0x28800000 Covered
+ , Encoding "STP_64_ldstpair_post" 0xbfc00000 0xa8800000 Covered
+ , Encoding "STP_32_ldstpair_pre" 0xbfc00000 0x29800000 Covered
+ , Encoding "STP_64_ldstpair_pre" 0xbfc00000 0xa9800000 Covered
+ , Encoding "STP_32_ldstpair_off" 0xbfc00000 0x29000000 Covered
+ , Encoding "STP_64_ldstpair_off" 0xbfc00000 0xa9000000 Covered
+ , Encoding "STR_B_ldst_immpost" 0xffa00c00 0x3c000400 Covered
+ , Encoding "STR_H_ldst_immpost" 0xffa00c00 0x7c000400 Covered
+ , Encoding "STR_S_ldst_immpost" 0xffa00c00 0xbc000400 Covered
+ , Encoding "STR_D_ldst_immpost" 0xffa00c00 0xfc000400 Covered
+ , Encoding "STR_Q_ldst_immpost" 0xffa00c00 0x3c800400 Covered
+ , Encoding "STR_B_ldst_immpre" 0xffa00c00 0x3c000c00 Covered
+ , Encoding "STR_H_ldst_immpre" 0xffa00c00 0x7c000c00 Covered
+ , Encoding "STR_S_ldst_immpre" 0xffa00c00 0xbc000c00 Covered
+ , Encoding "STR_D_ldst_immpre" 0xffa00c00 0xfc000c00 Covered
+ , Encoding "STR_Q_ldst_immpre" 0xffa00c00 0x3c800c00 Covered
+ , Encoding "STR_B_ldst_pos" 0xff800000 0x3d000000 Covered
+ , Encoding "STR_H_ldst_pos" 0xff800000 0x7d000000 Covered
+ , Encoding "STR_S_ldst_pos" 0xff800000 0xbd000000 Covered
+ , Encoding "STR_D_ldst_pos" 0xff800000 0xfd000000 Covered
+ , Encoding "STR_Q_ldst_pos" 0xff800000 0x3d800000 Covered
+ , Encoding "STR_32_ldst_immpost" 0x7fe00c00 0x38000400 Covered
+ , Encoding "STR_64_ldst_immpost" 0x7fe00c00 0x78000400 Covered
+ , Encoding "STR_32_ldst_immpre" 0x7fe00c00 0x38000c00 Covered
+ , Encoding "STR_64_ldst_immpre" 0x7fe00c00 0x78000c00 Covered
+ , Encoding "STR_32_ldst_pos" 0x7fc00000 0x39000000 Covered
+ , Encoding "STR_64_ldst_pos" 0x7fc00000 0x79000000 Covered
+ , Encoding "STR_B_ldst_regoff" 0xffa00c00 0x3c200800 Covered
+ , Encoding "STR_BL_ldst_regoff" 0xffa0ec00 0x3c206800 Covered
+ , Encoding "STR_H_ldst_regoff" 0xffa00c00 0x7c200800 Covered
+ , Encoding "STR_S_ldst_regoff" 0xffa00c00 0xbc200800 Covered
+ , Encoding "STR_D_ldst_regoff" 0xffa00c00 0xfc200800 Covered
+ , Encoding "STR_Q_ldst_regoff" 0xffa00c00 0x3ca00800 Covered
+ , Encoding "STR_32_ldst_regoff" 0x7fe00c00 0x38200800 Covered
+ , Encoding "STR_64_ldst_regoff" 0x7fe00c00 0x78200800 Covered
+ , Encoding "STRB_32_ldst_immpost" 0xffe00c00 0x38000400 Covered
+ , Encoding "STRB_32_ldst_immpre" 0xffe00c00 0x38000c00 Covered
+ , Encoding "STRB_32_ldst_pos" 0xffc00000 0x39000000 Covered
+ , Encoding "STRB_32B_ldst_regoff" 0xffe00c00 0x38200800 Covered
+ , Encoding "STRB_32BL_ldst_regoff" 0xffe0ec00 0x38206800 Covered
+ , Encoding "STRH_32_ldst_immpost" 0xffe00c00 0x78000400 Covered
+ , Encoding "STRH_32_ldst_immpre" 0xffe00c00 0x78000c00 Covered
+ , Encoding "STRH_32_ldst_pos" 0xffc00000 0x79000000 Covered
+ , Encoding "STRH_32_ldst_regoff" 0xffe00c00 0x78200800 Covered
+ , Encoding "STTR_32_ldst_unpriv" 0x7fe00c00 0x38000800 Covered
+ , Encoding "STTR_64_ldst_unpriv" 0x7fe00c00 0x78000800 Covered
+ , Encoding "STTRB_32_ldst_unpriv" 0xffe00c00 0x38000800 Covered
+ , Encoding "STTRH_32_ldst_unpriv" 0xffe00c00 0x78000800 Covered
+ , Encoding "STUR_B_ldst_unscaled" 0xffa00c00 0x3c000000 Covered
+ , Encoding "STUR_H_ldst_unscaled" 0xffa00c00 0x7c000000 Covered
+ , Encoding "STUR_S_ldst_unscaled" 0xffa00c00 0xbc000000 Covered
+ , Encoding "STUR_D_ldst_unscaled" 0xffa00c00 0xfc000000 Covered
+ , Encoding "STUR_Q_ldst_unscaled" 0xffa00c00 0x3c800000 Covered
+ , Encoding "STUR_32_ldst_unscaled" 0x7fe00c00 0x38000000 Covered
+ , Encoding "STUR_64_ldst_unscaled" 0x7fe00c00 0x78000000 Covered
+ , Encoding "STURB_32_ldst_unscaled" 0xffe00c00 0x38000000 Covered
+ , Encoding "STURH_32_ldst_unscaled" 0xffe00c00 0x78000000 Covered
+ , Encoding "STXP_SP32_ldstexclp" 0xffe08000 0x88200000 Covered
+ , Encoding "STXP_SP64_ldstexclp" 0xffe08000 0xc8200000 Covered
+ , Encoding "STXR_SR32_ldstexclr" 0x7fe08000 0x08000000 Covered
+ , Encoding "STXR_SR64_ldstexclr" 0x7fe08000 0x48000000 Covered
+ , Encoding "STXRB_SR32_ldstexclr" 0xffe08000 0x08000000 Covered
+ , Encoding "STXRH_SR32_ldstexclr" 0xffe08000 0x48000000 Covered
+ , Encoding "STZ2G_64Spost_ldsttags" 0xffe00c00 0xd9e00400
+ (Outside [(0, OpXSp)])
+ , Encoding "STZ2G_64Spre_ldsttags" 0xffe00c00 0xd9e00c00
+ (Outside [(0, OpXSp)])
+ , Encoding "STZ2G_64Soffset_ldsttags" 0xffe00c00 0xd9e00800
+ (Outside [(0, OpXSp)])
+ , Encoding "STZG_64Spost_ldsttags" 0xffe00c00 0xd9600400
+ (Outside [(0, OpXSp)])
+ , Encoding "STZG_64Spre_ldsttags" 0xffe00c00 0xd9600c00
+ (Outside [(0, OpXSp)])
+ , Encoding "STZG_64Soffset_ldsttags" 0xffe00c00 0xd9600800
+ (Outside [(0, OpXSp)])
+ , Encoding "STZGM_64bulk_ldsttags" 0xfffffc00 0xd9200000 (Outside [(0, OpX)])
+ , Encoding "SUB_32_addsub_ext" 0xffe00000 0x4b200000 Covered
+ , Encoding "SUB_64_addsub_ext" 0xffe00000 0xcb200000 Covered
+ , Encoding "SUB_32_addsub_imm" 0xff800000 0x51000000 Covered
+ , Encoding "SUB_64_addsub_imm" 0xff800000 0xd1000000 Covered
+ , Encoding "SUB_32_addsub_shift" 0xff200000 0x4b000000 Covered
+ , Encoding "SUB_64_addsub_shift" 0xff200000 0xcb000000 Covered
+ , Encoding "SUB_asisdsame_only" 0xff20fc00 0x7e208400 Covered
+ , Encoding "SUB_asimdsame_only" 0xbf20fc00 0x2e208400 Covered
+ , Encoding "SUBG_64_addsub_immtags" 0xffc00000 0xd1800000
+ (Outside [(5, OpXSp)])
+ , Encoding "SUBHN_asimddiff_N" 0xbf20fc00 0x0e206000 Covered
+ , Encoding "SUBP_64S_dp_2src" 0xffe0fc00 0x9ac00000
+ (Outside [(5, OpXSp), (16, OpXSp)])
+ , Encoding "SUBPS_64S_dp_2src" 0xffe0fc00 0xbac00000
+ (Outside [(5, OpXSp), (16, OpXSp)])
+ , Encoding "SUBS_32S_addsub_ext" 0xffe00000 0x6b200000 Covered
+ , Encoding "SUBS_64S_addsub_ext" 0xffe00000 0xeb200000 Covered
+ , Encoding "SUBS_32S_addsub_imm" 0xff800000 0x71000000 Covered
+ , Encoding "SUBS_64S_addsub_imm" 0xff800000 0xf1000000 Covered
+ , Encoding "SUBS_32_addsub_shift" 0xff200000 0x6b000000 Covered
+ , Encoding "SUBS_64_addsub_shift" 0xff200000 0xeb000000 Covered
+ , Encoding "SUDOT_asimdelem_D" 0xbfc0f400 0x0f00f000
+ (Outside [(0, OpV), (5, OpV)])
+ , Encoding "SUQADD_asisdmisc_R" 0xff3ffc00 0x5e203800 (Outside [])
+ , Encoding "SUQADD_asimdmisc_R" 0xbf3ffc00 0x0e203800 (Outside [(5, OpV)])
+ , Encoding "SVC_EX_exception" 0xffe0001f 0xd4000001 Control
+ , Encoding "SWP_32_memop" 0x7fe0fc00 0x38208000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPA_32_memop" 0x7fe0fc00 0x38a08000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPAL_32_memop" 0x7fe0fc00 0x38e08000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPL_32_memop" 0x7fe0fc00 0x38608000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWP_64_memop" 0x7fe0fc00 0x78208000
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "SWPA_64_memop" 0x7fe0fc00 0x78a08000
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "SWPAL_64_memop" 0x7fe0fc00 0x78e08000
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "SWPL_64_memop" 0x7fe0fc00 0x78608000
+ (Outside [(0, OpX), (16, OpX)])
+ , Encoding "SWPAB_32_memop" 0xffe0fc00 0x38a08000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPALB_32_memop" 0xffe0fc00 0x38e08000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPB_32_memop" 0xffe0fc00 0x38208000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPLB_32_memop" 0xffe0fc00 0x38608000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPAH_32_memop" 0xffe0fc00 0x78a08000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPALH_32_memop" 0xffe0fc00 0x78e08000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPH_32_memop" 0xffe0fc00 0x78208000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPLH_32_memop" 0xffe0fc00 0x78608000
+ (Outside [(0, OpW), (16, OpW)])
+ , Encoding "SWPP_128_memop_128" 0xffe0fc00 0x19208000 Covered
+ , Encoding "SWPPA_128_memop_128" 0xffe0fc00 0x19a08000 Covered
+ , Encoding "SWPPAL_128_memop_128" 0xffe0fc00 0x19e08000 Covered
+ , Encoding "SWPPL_128_memop_128" 0xffe0fc00 0x19608000 Covered
+ , Encoding "SYS_CR_systeminstrs" 0xfff80000 0xd5080000 Control
+ , Encoding "SYSL_RC_systeminstrs" 0xfff80000 0xd5280000 Control
+ , Encoding "SYSP_CR_syspairinstrs" 0xfff80000 0xd5480000 Control
+ , Encoding "TBL_asimdtbl_L2_2" 0xbfe0fc00 0x0e002000 Covered
+ , Encoding "TBL_asimdtbl_L3_3" 0xbfe0fc00 0x0e004000 Covered
+ , Encoding "TBL_asimdtbl_L4_4" 0xbfe0fc00 0x0e006000 Covered
+ , Encoding "TBL_asimdtbl_L1_1" 0xbfe0fc00 0x0e000000 Covered
+ , Encoding "TBNZ_only_testbranch" 0x7f000000 0x37000000 Control
+ , Encoding "TBX_asimdtbl_L2_2" 0xbfe0fc00 0x0e003000 Covered
+ , Encoding "TBX_asimdtbl_L3_3" 0xbfe0fc00 0x0e005000 Covered
+ , Encoding "TBX_asimdtbl_L4_4" 0xbfe0fc00 0x0e007000 Covered
+ , Encoding "TBX_asimdtbl_L1_1" 0xbfe0fc00 0x0e001000 Covered
+ , Encoding "TBZ_only_testbranch" 0x7f000000 0x36000000 Control
+ , Encoding "TCANCEL_EX_exception" 0xffe0001f 0xd4600000 Control
+ , Encoding "TCOMMIT_only_barriers" 0xffffffff 0xd503307f Control
+ , Encoding "TRN1_asimdperm_only" 0xbf20fc00 0x0e002800 Covered
+ , Encoding "TRN2_asimdperm_only" 0xbf20fc00 0x0e006800 Covered
+ , Encoding "TSB_HC_hints" 0xffffffff 0xd503225f Control
+ , Encoding "TSTART_BR_systemresult" 0xffffffe0 0xd5233060 Control
+ , Encoding "TTEST_BR_systemresult" 0xffffffe0 0xd5233160 Control
+ , Encoding "UABA_asimdsame_only" 0xbf20fc00 0x2e207c00 Covered
+ , Encoding "UABAL_asimddiff_L" 0xbf20fc00 0x2e205000 Covered
+ , Encoding "UABD_asimdsame_only" 0xbf20fc00 0x2e207400 Covered
+ , Encoding "UABDL_asimddiff_L" 0xbf20fc00 0x2e207000 Covered
+ , Encoding "UADALP_asimdmisc_P" 0xbf3ffc00 0x2e206800 Covered
+ , Encoding "UADDL_asimddiff_L" 0xbf20fc00 0x2e200000 Covered
+ , Encoding "UADDLP_asimdmisc_P" 0xbf3ffc00 0x2e202800 Covered
+ , Encoding "UADDLV_asimdall_only" 0xbf3ffc00 0x2e303800 Covered
+ , Encoding "UADDW_asimddiff_W" 0xbf20fc00 0x2e201000 Covered
+ , Encoding "UBFM_32M_bitfield" 0xffc00000 0x53000000 Covered
+ , Encoding "UBFM_64M_bitfield" 0xffc00000 0xd3400000 Covered
+ , Encoding "UCVTF_asisdshf_C" 0xff80fc00 0x7f00e400 (Outside [])
+ , Encoding "UCVTF_asimdshf_C" 0xbf80fc00 0x2f00e400 (Outside [(5, OpV)])
+ , Encoding "UCVTF_asisdmiscfp16_R" 0xfffffc00 0x7e79d800 (Outside [(5, OpH)])
+ , Encoding "UCVTF_asisdmisc_R" 0xffbffc00 0x7e21d800 (Outside [])
+ , Encoding "UCVTF_asimdmiscfp16_R" 0xbffffc00 0x2e79d800 (Outside [(5, OpV)])
+ , Encoding "UCVTF_asimdmisc_R" 0xbfbffc00 0x2e21d800 (Outside [(5, OpV)])
+ , Encoding "UCVTF_H32_float2fix" 0xffff0000 0x1ec30000 (Outside [(5, OpW)])
+ , Encoding "UCVTF_S32_float2fix" 0xffff0000 0x1e030000 (Outside [(5, OpW)])
+ , Encoding "UCVTF_D32_float2fix" 0xffff0000 0x1e430000 (Outside [(5, OpW)])
+ , Encoding "UCVTF_H64_float2fix" 0xffff0000 0x9ec30000 (Outside [(5, OpX)])
+ , Encoding "UCVTF_S64_float2fix" 0xffff0000 0x9e030000 (Outside [(5, OpX)])
+ , Encoding "UCVTF_D64_float2fix" 0xffff0000 0x9e430000 (Outside [(5, OpX)])
+ , Encoding "UCVTF_H32_float2int" 0xfffffc00 0x1ee30000 (Outside [(5, OpW)])
+ , Encoding "UCVTF_S32_float2int" 0xfffffc00 0x1e230000 (Outside [(5, OpW)])
+ , Encoding "UCVTF_D32_float2int" 0xfffffc00 0x1e630000 (Outside [(5, OpW)])
+ , Encoding "UCVTF_H64_float2int" 0xfffffc00 0x9ee30000 (Outside [(5, OpX)])
+ , Encoding "UCVTF_S64_float2int" 0xfffffc00 0x9e230000 (Outside [(5, OpX)])
+ , Encoding "UCVTF_D64_float2int" 0xfffffc00 0x9e630000 (Outside [(5, OpX)])
+ , Encoding "UDF_only_perm_undef" 0xffff0000 0x00000000 (Outside [])
+ , Encoding "UDIV_32_dp_2src" 0xffe0fc00 0x1ac00800
+ (Outside [(5, OpW), (16, OpW)])
+ , Encoding "UDIV_64_dp_2src" 0xffe0fc00 0x9ac00800
+ (Outside [(5, OpX), (16, OpX)])
+ , Encoding "UDOT_asimdelem_D" 0xbf00f400 0x2f00e000
+ (Outside [(0, OpV), (5, OpV)])
+ , Encoding "UDOT_asimdsame2_D" 0xbf20fc00 0x2e009400
+ (Outside [(0, OpV), (5, OpV), (16, OpV)])
+ , Encoding "UHADD_asimdsame_only" 0xbf20fc00 0x2e200400 Covered
+ , Encoding "UHSUB_asimdsame_only" 0xbf20fc00 0x2e202400 Covered
+ , Encoding "UMADDL_64WA_dp_3src" 0xffe08000 0x9ba00000 Covered
+ , Encoding "UMAX_asimdsame_only" 0xbf20fc00 0x2e206400 Covered
+ , Encoding "UMAX_32U_minmax_imm" 0xfffc0000 0x11c40000 Covered
+ , Encoding "UMAX_64U_minmax_imm" 0xfffc0000 0x91c40000 Covered
+ , Encoding "UMAX_32_dp_2src" 0xffe0fc00 0x1ac06400 Covered
+ , Encoding "UMAX_64_dp_2src" 0xffe0fc00 0x9ac06400 Covered
+ , Encoding "UMAXP_asimdsame_only" 0xbf20fc00 0x2e20a400 Covered
+ , Encoding "UMAXV_asimdall_only" 0xbf3ffc00 0x2e30a800 Covered
+ , Encoding "UMIN_asimdsame_only" 0xbf20fc00 0x2e206c00 Covered
+ , Encoding "UMIN_32U_minmax_imm" 0xfffc0000 0x11cc0000 Covered
+ , Encoding "UMIN_64U_minmax_imm" 0xfffc0000 0x91cc0000 Covered
+ , Encoding "UMIN_32_dp_2src" 0xffe0fc00 0x1ac06c00 Covered
+ , Encoding "UMIN_64_dp_2src" 0xffe0fc00 0x9ac06c00 Covered
+ , Encoding "UMINP_asimdsame_only" 0xbf20fc00 0x2e20ac00 Covered
+ , Encoding "UMINV_asimdall_only" 0xbf3ffc00 0x2e31a800 Covered
+ , Encoding "UMLAL_asimdelem_L" 0xbf00f400 0x2f002000 Covered
+ , Encoding "UMLAL_asimddiff_L" 0xbf20fc00 0x2e208000 Covered
+ , Encoding "UMLSL_asimdelem_L" 0xbf00f400 0x2f006000 Covered
+ , Encoding "UMLSL_asimddiff_L" 0xbf20fc00 0x2e20a000 Covered
+ , Encoding "UMMLA_asimdsame2_G" 0xffe0fc00 0x6e80a400
+ (Outside [(0, OpV), (5, OpV), (16, OpV)])
+ , Encoding "UMOV_asimdins_W_w" 0xffe0fc00 0x0e003c00 Covered
+ , Encoding "UMOV_asimdins_X_x" 0xffeffc00 0x4e083c00 Covered
+ , Encoding "UMSUBL_64WA_dp_3src" 0xffe08000 0x9ba08000 Covered
+ , Encoding "UMULH_64_dp_3src" 0xffe08000 0x9bc00000 Covered
+ , Encoding "UMULL_asimdelem_L" 0xbf00f400 0x2f00a000 Covered
+ , Encoding "UMULL_asimddiff_L" 0xbf20fc00 0x2e20c000 Covered
+ , Encoding "UQADD_asisdsame_only" 0xff20fc00 0x7e200c00 (Outside [])
+ , Encoding "UQADD_asimdsame_only" 0xbf20fc00 0x2e200c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "UQRSHL_asisdsame_only" 0xff20fc00 0x7e205c00 (Outside [])
+ , Encoding "UQRSHL_asimdsame_only" 0xbf20fc00 0x2e205c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "UQRSHRN_asisdshf_N" 0xff80fc00 0x7f009c00 (Outside [])
+ , Encoding "UQRSHRN_asimdshf_N" 0xbf80fc00 0x2f009c00 (Outside [(5, OpV)])
+ , Encoding "UQSHL_asisdshf_R" 0xff80fc00 0x7f007400 (Outside [])
+ , Encoding "UQSHL_asimdshf_R" 0xbf80fc00 0x2f007400 (Outside [(5, OpV)])
+ , Encoding "UQSHL_asisdsame_only" 0xff20fc00 0x7e204c00 (Outside [])
+ , Encoding "UQSHL_asimdsame_only" 0xbf20fc00 0x2e204c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "UQSHRN_asisdshf_N" 0xff80fc00 0x7f009400 (Outside [])
+ , Encoding "UQSHRN_asimdshf_N" 0xbf80fc00 0x2f009400 (Outside [(5, OpV)])
+ , Encoding "UQSUB_asisdsame_only" 0xff20fc00 0x7e202c00 (Outside [])
+ , Encoding "UQSUB_asimdsame_only" 0xbf20fc00 0x2e202c00
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "UQXTN_asisdmisc_N" 0xff3ffc00 0x7e214800 (Outside [])
+ , Encoding "UQXTN_asimdmisc_N" 0xbf3ffc00 0x2e214800 (Outside [(5, OpV)])
+ , Encoding "URECPE_asimdmisc_R" 0xbfbffc00 0x0ea1c800 (Outside [(5, OpV)])
+ , Encoding "URHADD_asimdsame_only" 0xbf20fc00 0x2e201400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "URSHL_asisdsame_only" 0xff20fc00 0x7e205400 (Outside [])
+ , Encoding "URSHL_asimdsame_only" 0xbf20fc00 0x2e205400
+ (Outside [(5, OpV), (16, OpV)])
+ , Encoding "URSHR_asisdshf_R" 0xff80fc00 0x7f002400 (Outside [])
+ , Encoding "URSHR_asimdshf_R" 0xbf80fc00 0x2f002400 (Outside [(5, OpV)])
+ , Encoding "URSQRTE_asimdmisc_R" 0xbfbffc00 0x2ea1c800 (Outside [(5, OpV)])
+ , Encoding "URSRA_asisdshf_R" 0xff80fc00 0x7f003400 (Outside [])
+ , Encoding "URSRA_asimdshf_R" 0xbf80fc00 0x2f003400 (Outside [(5, OpV)])
+ , Encoding "USDOT_asimdelem_D" 0xbfc0f400 0x0f80f000
+ (Outside [(0, OpV), (5, OpV)])
+ , Encoding "USDOT_asimdsame2_D" 0xbfe0fc00 0x0e809c00
+ (Outside [(0, OpV), (5, OpV), (16, OpV)])
+ , Encoding "USHL_asisdsame_only" 0xff20fc00 0x7e204400 Covered
+ , Encoding "USHL_asimdsame_only" 0xbf20fc00 0x2e204400 Covered
+ , Encoding "USHLL_asimdshf_L" 0xbf80fc00 0x2f00a400 Covered
+ , Encoding "USHR_asisdshf_R" 0xff80fc00 0x7f000400 Covered
+ , Encoding "USHR_asimdshf_R" 0xbf80fc00 0x2f000400 Covered
+ , Encoding "USMMLA_asimdsame2_G" 0xffe0fc00 0x4e80ac00
+ (Outside [(0, OpV), (5, OpV), (16, OpV)])
+ , Encoding "USQADD_asisdmisc_R" 0xff3ffc00 0x7e203800 (Outside [])
+ , Encoding "USQADD_asimdmisc_R" 0xbf3ffc00 0x2e203800 (Outside [(5, OpV)])
+ , Encoding "USRA_asisdshf_R" 0xff80fc00 0x7f001400 Covered
+ , Encoding "USRA_asimdshf_R" 0xbf80fc00 0x2f001400 Covered
+ , Encoding "USUBL_asimddiff_L" 0xbf20fc00 0x2e202000 Covered
+ , Encoding "USUBW_asimddiff_W" 0xbf20fc00 0x2e203000 Covered
+ , Encoding "UZP1_asimdperm_only" 0xbf20fc00 0x0e001800 Covered
+ , Encoding "UZP2_asimdperm_only" 0xbf20fc00 0x0e005800 Covered
+ , Encoding "WFE_HI_hints" 0xffffffff 0xd503205f Control
+ , Encoding "WFET_only_systeminstrswithreg" 0xffffffe0 0xd5031000 Control
+ , Encoding "WFI_HI_hints" 0xffffffff 0xd503207f Control
+ , Encoding "WFIT_only_systeminstrswithreg" 0xffffffe0 0xd5031020 Control
+ , Encoding "XAFLAG_M_pstate" 0xfffff0ff 0xd500403f Control
+ , Encoding "XAR_VVV2_crypto3_imm6" 0xffe00000 0xce800000 Covered
+ , Encoding "XPACD_64Z_dp_1src" 0xffffffe0 0xdac147e0 (Outside [])
+ , Encoding "XPACI_64Z_dp_1src" 0xffffffe0 0xdac143e0 (Outside [])
+ , Encoding "XPACLRI_HI_hints" 0xffffffff 0xd50320ff (Outside [])
+ , Encoding "XTN_asimdmisc_N" 0xbf3ffc00 0x0e212800 Covered
+ , Encoding "YIELD_HI_hints" 0xffffffff 0xd503203f Control
+ , Encoding "ZIP1_asimdperm_only" 0xbf20fc00 0x0e003800 Covered
+ , Encoding "ZIP2_asimdperm_only" 0xbf20fc00 0x0e007800 Covered
+ ]
diff --git a/lib/Vestigia/Contract/Intel.hs b/lib/Vestigia/Contract/Intel.hs
@@ -0,0 +1,282 @@
+{-# OPTIONS_HADDOCK prune #-}
+{-# LANGUAGE OverloadedStrings #-}
+
+-- |
+-- Module: Vestigia.Contract.Intel
+-- Copyright: (c) 2026 Jared Tobin
+-- License: MIT
+-- Maintainer: Jared Tobin <jared@ppad.tech>
+--
+-- Intel's data-operand-independent-timing contract (DOITM), row by
+-- row, transcribed from Intel's list.
+--
+-- == Source
+--
+-- Intel, /Data Operand Independent Timing Instructions/, document ID
+-- 768547, updated 2026-02-23, Table 1 \"Documented Data Operand
+-- Independent Timing Instructions\" (840 mnemonic\/opcode rows, 594
+-- distinct mnemonics), retrieved 2026-10-27 from @www.intel.com@
+-- under
+-- @\/content\/www\/us\/en\/developer\/articles\/technical\/@
+-- @software-security-guidance\/resources\/@, saved from a browser
+-- (the host refuses automated retrieval; sha256 of the page as saved
+-- @0f67179a44c9f872ab240c3363ee664340beea36ce4a07cbfe1a34cc7adb6a10@).
+-- The revision of 2023-02-28, as the Internet Archive kept it through
+-- 2025-11-13, lacks BSWAP, CQO, MOVAPS, MOVSS, MOVUPS, ROL, ROR,
+-- RORX, SHLD, SHRD, and XORPS; this one adds them and drops none.
+--
+-- == Rule
+--
+-- A row names a mnemonic and an opcode byte: the instruction's last
+-- opcode byte, after any prefixes, VEX or EVEX payload, and escape
+-- bytes. The list's own preface reads:
+--
+-- > The table below lists instructions that have data-independent
+-- > timing. [...] Note that these data operand independent timing
+-- > instructions may have variable latency for reasons unrelated to
+-- > the data values (for example, loading data from memory or the
+-- > encoding of the instruction).
+--
+-- The @REP_@ rows carry a footnote, \"These REP_ instructions'
+-- latency varies based on the loop count (*CX)\", whose marker is
+-- dropped from their names here: a count that depends on the secret
+-- repeats the instruction a different number of times, which is
+-- control flow.
+
+module Vestigia.Contract.Intel (
+ instructions
+ ) where
+
+import qualified Data.Text as T
+import Data.Word (Word8)
+
+-- | Every row: a mnemonic, as the list spells it, and an opcode byte.
+instructions :: [(T.Text, Word8)]
+instructions =
+ [ ("ADC", 0x10), ("ADC", 0x11), ("ADC", 0x12), ("ADC", 0x13), ("ADC", 0x14)
+ , ("ADC", 0x15), ("ADC", 0x80), ("ADC", 0x81), ("ADC", 0x82), ("ADC", 0x83)
+ , ("ADCX", 0xf6), ("ADD", 0x00), ("ADD", 0x01), ("ADD", 0x02), ("ADD", 0x03)
+ , ("ADD", 0x04), ("ADD", 0x05), ("ADD", 0x80), ("ADD", 0x81), ("ADD", 0x82)
+ , ("ADD", 0x83), ("ADOX", 0xf6), ("AESDEC", 0xde), ("AESDECLAST", 0xdf)
+ , ("AESENC", 0xdc), ("AESENCLAST", 0xdd), ("AESIMC", 0xdb)
+ , ("AESKEYGENASSIST", 0xdf), ("AND", 0x20), ("AND", 0x21), ("AND", 0x22)
+ , ("AND", 0x23), ("AND", 0x24), ("AND", 0x25), ("AND", 0x80), ("AND", 0x81)
+ , ("AND", 0x82), ("AND", 0x83), ("ANDN", 0xf2), ("BSWAP", 0xc8)
+ , ("BSWAP", 0xc9), ("BSWAP", 0xca), ("BSWAP", 0xcb), ("BSWAP", 0xcc)
+ , ("BSWAP", 0xcd), ("BSWAP", 0xce), ("BSWAP", 0xcf), ("BT", 0xa3)
+ , ("BT", 0xba), ("BTC", 0xba), ("BTC", 0xbb), ("BTR", 0xb3), ("BTR", 0xba)
+ , ("BTS", 0xab), ("BTS", 0xba), ("CMOVB", 0x42), ("CMOVBE", 0x46)
+ , ("CMOVL", 0x4c), ("CMOVLE", 0x4e), ("CMOVNB", 0x43), ("CMOVNBE", 0x47)
+ , ("CMOVNL", 0x4d), ("CMOVNLE", 0x4f), ("CMOVNO", 0x41), ("CMOVNP", 0x4b)
+ , ("CMOVNS", 0x49), ("CMOVNZ", 0x45), ("CMOVO", 0x40), ("CMOVP", 0x4a)
+ , ("CMOVS", 0x48), ("CMOVZ", 0x44), ("CMP", 0x38), ("CMP", 0x39)
+ , ("CMP", 0x3a), ("CMP", 0x3b), ("CMP", 0x3c), ("CMP", 0x3d), ("CMP", 0x80)
+ , ("CMP", 0x81), ("CMP", 0x82), ("CMP", 0x83), ("CQO", 0x99), ("DEC", 0x48)
+ , ("DEC", 0x49), ("DEC", 0x4a), ("DEC", 0x4b), ("DEC", 0x4c), ("DEC", 0x4d)
+ , ("DEC", 0x4e), ("DEC", 0x4f), ("DEC", 0xfe), ("DEC", 0xff)
+ , ("GF2P8AFFINEINVQB", 0xcf), ("GF2P8AFFINEQB", 0xce), ("GF2P8MULB", 0xcf)
+ , ("IMUL", 0x69), ("IMUL", 0x6b), ("IMUL", 0xaf), ("IMUL", 0xf6)
+ , ("IMUL", 0xf7), ("INC", 0x40), ("INC", 0x41), ("INC", 0x42), ("INC", 0x43)
+ , ("INC", 0x44), ("INC", 0x45), ("INC", 0x46), ("INC", 0x47), ("INC", 0xfe)
+ , ("INC", 0xff), ("KADDB", 0x4a), ("KADDD", 0x4a), ("KADDQ", 0x4a)
+ , ("KADDW", 0x4a), ("KANDB", 0x41), ("KANDD", 0x41), ("KANDNB", 0x42)
+ , ("KANDND", 0x42), ("KANDNQ", 0x42), ("KANDNW", 0x42), ("KANDQ", 0x41)
+ , ("KANDW", 0x41), ("KMOVB", 0x90), ("KMOVB", 0x91), ("KMOVB", 0x92)
+ , ("KMOVB", 0x93), ("KMOVD", 0x90), ("KMOVD", 0x91), ("KMOVD", 0x92)
+ , ("KMOVD", 0x93), ("KMOVQ", 0x90), ("KMOVQ", 0x91), ("KMOVQ", 0x92)
+ , ("KMOVQ", 0x93), ("KMOVW", 0x90), ("KMOVW", 0x91), ("KMOVW", 0x92)
+ , ("KMOVW", 0x93), ("KNOTB", 0x44), ("KNOTD", 0x44), ("KNOTQ", 0x44)
+ , ("KNOTW", 0x44), ("KORB", 0x45), ("KORD", 0x45), ("KORQ", 0x45)
+ , ("KORTESTB", 0x98), ("KORTESTD", 0x98), ("KORTESTQ", 0x98)
+ , ("KORTESTW", 0x98), ("KORW", 0x45), ("KSHIFTLB", 0x32), ("KSHIFTLD", 0x33)
+ , ("KSHIFTLQ", 0x33), ("KSHIFTLW", 0x32), ("KSHIFTRB", 0x30)
+ , ("KSHIFTRD", 0x31), ("KSHIFTRQ", 0x31), ("KSHIFTRW", 0x30)
+ , ("KTESTB", 0x99), ("KTESTD", 0x99), ("KTESTQ", 0x99), ("KTESTW", 0x99)
+ , ("KUNPCKBW", 0x4b), ("KUNPCKDQ", 0x4b), ("KUNPCKWD", 0x4b)
+ , ("KXNORB", 0x46), ("KXNORD", 0x46), ("KXNORQ", 0x46), ("KXNORW", 0x46)
+ , ("KXORB", 0x47), ("KXORD", 0x47), ("KXORQ", 0x47), ("KXORW", 0x47)
+ , ("LDDQU", 0xf0), ("LEA", 0x8d), ("MOV", 0x88), ("MOV", 0x89), ("MOV", 0x8a)
+ , ("MOV", 0x8b), ("MOV", 0xa0), ("MOV", 0xa1), ("MOV", 0xa2), ("MOV", 0xa3)
+ , ("MOV", 0xb0), ("MOV", 0xb1), ("MOV", 0xb2), ("MOV", 0xb3), ("MOV", 0xb4)
+ , ("MOV", 0xb5), ("MOV", 0xb6), ("MOV", 0xb7), ("MOV", 0xb8), ("MOV", 0xb9)
+ , ("MOV", 0xba), ("MOV", 0xbb), ("MOV", 0xbc), ("MOV", 0xbd), ("MOV", 0xbe)
+ , ("MOV", 0xbf), ("MOV", 0xc6), ("MOV", 0xc7), ("MOVAPS", 0x28)
+ , ("MOVAPS", 0x29), ("MOVD", 0x6e), ("MOVD", 0x7e), ("MOVDDUP", 0x12)
+ , ("MOVDQ2Q", 0xd6), ("MOVDQA", 0x6f), ("MOVDQA", 0x7f), ("MOVDQU", 0x6f)
+ , ("MOVDQU", 0x7f), ("MOVNTDQ", 0xe7), ("MOVNTDQA", 0x2a), ("MOVQ", 0x6e)
+ , ("MOVQ", 0x7e), ("MOVQ", 0xd6), ("MOVSB", 0xa4), ("MOVSD", 0xa5)
+ , ("MOVSHDUP", 0x16), ("MOVSLDUP", 0x12), ("MOVSQ", 0xa5), ("MOVSS", 0x10)
+ , ("MOVSS", 0x11), ("MOVSW", 0xa5), ("MOVSX", 0xbe), ("MOVSX", 0xbf)
+ , ("MOVSXD", 0x63), ("MOVUPS", 0x10), ("MOVUPS", 0x11), ("MOVZX", 0xb6)
+ , ("MOVZX", 0xb7), ("MPSADBW", 0x42), ("MUL", 0xf6), ("MUL", 0xf7)
+ , ("MULX", 0xf6), ("NEG", 0xf6), ("NEG", 0xf7), ("NOT", 0xf6), ("NOT", 0xf7)
+ , ("OR", 0x08), ("OR", 0x80), ("OR", 0x81), ("OR", 0x82), ("OR", 0x83)
+ , ("OR", 0x09), ("OR", 0x0a), ("OR", 0x0b), ("OR", 0x0c), ("OR", 0x0d)
+ , ("PABSB", 0x1c), ("PABSD", 0x1e), ("PABSW", 0x1d), ("PACKSSDW", 0x6b)
+ , ("PACKSSWB", 0x63), ("PACKUSDW", 0x2b), ("PACKUSWB", 0x67), ("PADDB", 0xfc)
+ , ("PADDD", 0xfe), ("PADDQ", 0xd4), ("PADDSB", 0xec), ("PADDSW", 0xed)
+ , ("PADDUSB", 0xdc), ("PADDUSW", 0xdd), ("PADDW", 0xfd), ("PALIGNR", 0x0f)
+ , ("PAND", 0xdb), ("PANDN", 0xdf), ("PAVGB", 0xe0), ("PAVGW", 0xe3)
+ , ("PBLENDVB", 0x10), ("PBLENDW", 0x0e), ("PCLMULQDQ", 0x44)
+ , ("PCMPEQB", 0x74), ("PCMPEQD", 0x76), ("PCMPEQQ", 0x29), ("PCMPEQW", 0x75)
+ , ("PCMPGTB", 0x64), ("PCMPGTD", 0x66), ("PCMPGTQ", 0x37), ("PCMPGTW", 0x65)
+ , ("PEXTRB", 0x14), ("PEXTRD", 0x16), ("PEXTRQ", 0x16), ("PEXTRW", 0x15)
+ , ("PEXTRW", 0xc5), ("PHADDD", 0x02), ("PHADDSW", 0x03), ("PHADDW", 0x01)
+ , ("PHMINPOSUW", 0x41), ("PHSUBD", 0x06), ("PHSUBSW", 0x07), ("PHSUBW", 0x05)
+ , ("PINSRB", 0x20), ("PINSRD", 0x22), ("PINSRQ", 0x22), ("PINSRW", 0xc4)
+ , ("PMADDUBSW", 0x04), ("PMADDWD", 0xf5), ("PMAXSB", 0x3c), ("PMAXSW", 0xee)
+ , ("PMAXUB", 0xde), ("PMAXUD", 0x3f), ("PMAXUW", 0x3e), ("PMINSB", 0x38)
+ , ("PMINSW", 0xea), ("PMINUB", 0xda), ("PMINUD", 0x3b), ("PMINUW", 0x3a)
+ , ("PMOVMSKB", 0xd7), ("PMOVSXBD", 0x21), ("PMOVSXBQ", 0x22)
+ , ("PMOVSXBW", 0x20), ("PMOVSXDQ", 0x25), ("PMOVSXWD", 0x23)
+ , ("PMOVSXWQ", 0x24), ("PMOVZXBD", 0x31), ("PMOVZXBQ", 0x32)
+ , ("PMOVZXBW", 0x30), ("PMOVZXDQ", 0x35), ("PMOVZXWD", 0x33)
+ , ("PMOVZXWQ", 0x34), ("PMULDQ", 0x28), ("PMULHRSW", 0x0b), ("PMULHUW", 0xe4)
+ , ("PMULHW", 0xe5), ("PMULLD", 0x40), ("PMULLW", 0xd5), ("PMULUDQ", 0xf4)
+ , ("POP", 0x58), ("POP", 0x59), ("POP", 0x5a), ("POP", 0x5b), ("POP", 0x5c)
+ , ("POP", 0x5d), ("POP", 0x5e), ("POP", 0x5f), ("POP", 0x8f), ("POR", 0xeb)
+ , ("PSADBW", 0xf6), ("PSHUFB", 0x00), ("PSHUFD", 0x70), ("PSHUFHW", 0x70)
+ , ("PSHUFLW", 0x70), ("PSIGNB", 0x08), ("PSIGND", 0x0a), ("PSIGNW", 0x09)
+ , ("PSLLD", 0x72), ("PSLLD", 0xf2), ("PSLLDQ", 0x73), ("PSLLQ", 0x73)
+ , ("PSLLQ", 0xf3), ("PSLLW", 0x71), ("PSLLW", 0xf1), ("PSRAD", 0x72)
+ , ("PSRAD", 0xe2), ("PSRAW", 0x71), ("PSRAW", 0xe1), ("PSRLD", 0x72)
+ , ("PSRLD", 0xd2), ("PSRLDQ", 0x73), ("PSRLQ", 0x73), ("PSRLQ", 0xd3)
+ , ("PSRLW", 0x71), ("PSRLW", 0xd1), ("PSUBB", 0xf8), ("PSUBD", 0xfa)
+ , ("PSUBQ", 0xfb), ("PSUBSB", 0xe8), ("PSUBSW", 0xe9), ("PSUBUSB", 0xd8)
+ , ("PSUBUSW", 0xd9), ("PSUBW", 0xf9), ("PTEST", 0x17), ("PUNPCKHBW", 0x68)
+ , ("PUNPCKHDQ", 0x6a), ("PUNPCKHQDQ", 0x6d), ("PUNPCKHWD", 0x69)
+ , ("PUNPCKLBW", 0x60), ("PUNPCKLDQ", 0x62), ("PUNPCKLQDQ", 0x6c)
+ , ("PUNPCKLWD", 0x61), ("PUSH", 0x50), ("PUSH", 0x51), ("PUSH", 0x52)
+ , ("PUSH", 0x53), ("PUSH", 0x54), ("PUSH", 0x55), ("PUSH", 0x56)
+ , ("PUSH", 0x57), ("PUSH", 0x68), ("PUSH", 0x6a), ("PUSH", 0xff)
+ , ("PXOR", 0xef), ("REP_MOVSB", 0xa4), ("REP_MOVSD", 0xa5)
+ , ("REP_MOVSW", 0xa5), ("REP_STOSB", 0xaa), ("REP_STOSD", 0xab)
+ , ("REP_STOSW", 0xab), ("ROL", 0xc0), ("ROL", 0xc1), ("ROL", 0xd0)
+ , ("ROL", 0xd1), ("ROL", 0xd2), ("ROL", 0xd3), ("ROR", 0xc0), ("ROR", 0xc1)
+ , ("ROR", 0xd0), ("ROR", 0xd1), ("ROR", 0xd2), ("ROR", 0xd3), ("RORX", 0xf0)
+ , ("SAR", 0xc0), ("SAR", 0xc1), ("SAR", 0xd0), ("SAR", 0xd1), ("SAR", 0xd2)
+ , ("SAR", 0xd3), ("SBB", 0x18), ("SBB", 0x19), ("SBB", 0x1a), ("SBB", 0x1b)
+ , ("SBB", 0x1c), ("SBB", 0x1d), ("SBB", 0x80), ("SBB", 0x81), ("SBB", 0x82)
+ , ("SBB", 0x83), ("SETB", 0x92), ("SETBE", 0x96), ("SETL", 0x9c)
+ , ("SETLE", 0x9e), ("SETNB", 0x93), ("SETNBE", 0x97), ("SETNL", 0x9d)
+ , ("SETNLE", 0x9f), ("SETNO", 0x91), ("SETNP", 0x9b), ("SETNS", 0x99)
+ , ("SETNZ", 0x95), ("SETO", 0x90), ("SETP", 0x9a), ("SETS", 0x98)
+ , ("SETZ", 0x94), ("SHA1MSG1", 0xc9), ("SHA1MSG2", 0xca), ("SHA1NEXTE", 0xc8)
+ , ("SHA1RNDS4", 0xcc), ("SHA256MSG1", 0xcc), ("SHA256MSG2", 0xcd)
+ , ("SHA256RNDS2", 0xcb), ("SHL", 0xc0), ("SHL", 0xc1), ("SHL", 0xd0)
+ , ("SHL", 0xd1), ("SHL", 0xd2), ("SHL", 0xd3), ("SHLD", 0x24), ("SHLD", 0xa4)
+ , ("SHLD", 0xa5), ("SHLX", 0xf7), ("SHR", 0xc0), ("SHR", 0xc1), ("SHR", 0xd0)
+ , ("SHR", 0xd1), ("SHR", 0xd2), ("SHR", 0xd3), ("SHRD", 0x2c), ("SHRD", 0xac)
+ , ("SHRD", 0xad), ("SHRX", 0xf7), ("SUB", 0x28), ("SUB", 0x29), ("SUB", 0x2a)
+ , ("SUB", 0x2b), ("SUB", 0x2c), ("SUB", 0x2d), ("SUB", 0x80), ("SUB", 0x81)
+ , ("SUB", 0x82), ("SUB", 0x83), ("TEST", 0x84), ("TEST", 0x85)
+ , ("TEST", 0xa8), ("TEST", 0xa9), ("TEST", 0xf6), ("TEST", 0xf7)
+ , ("VAESDEC", 0xde), ("VAESDECLAST", 0xdf), ("VAESENC", 0xdc)
+ , ("VAESENCLAST", 0xdd), ("VAESIMC", 0xdb), ("VAESKEYGENASSIST", 0xdf)
+ , ("VALIGND", 0x03), ("VALIGNQ", 0x03), ("VBLENDMPD", 0x65)
+ , ("VBLENDMPS", 0x65), ("VBROADCASTF128", 0x1a), ("VBROADCASTF32X2", 0x19)
+ , ("VBROADCASTF32X4", 0x1a), ("VBROADCASTF32X8", 0x1b)
+ , ("VBROADCASTF64X2", 0x1a), ("VBROADCASTF64X4", 0x1b)
+ , ("VBROADCASTI128", 0x5a), ("VBROADCASTI32X2", 0x59)
+ , ("VBROADCASTI32X4", 0x5a), ("VBROADCASTI32X8", 0x5b)
+ , ("VBROADCASTI64X2", 0x5a), ("VBROADCASTI64X4", 0x5b)
+ , ("VBROADCASTSD", 0x19), ("VBROADCASTSS", 0x18), ("VCOMPRESSPD", 0x8a)
+ , ("VCOMPRESSPS", 0x8a), ("VDBPSADBW", 0x42), ("VEXPANDPD", 0x88)
+ , ("VEXPANDPS", 0x88), ("VEXTRACTF128", 0x19), ("VEXTRACTF32X4", 0x19)
+ , ("VEXTRACTF32X8", 0x1b), ("VEXTRACTF64X2", 0x19), ("VEXTRACTF64X4", 0x1b)
+ , ("VEXTRACTI128", 0x39), ("VEXTRACTI32X4", 0x39), ("VEXTRACTI32X8", 0x3b)
+ , ("VEXTRACTI64X2", 0x39), ("VEXTRACTI64X4", 0x3b)
+ , ("VGF2P8AFFINEINVQB", 0xcf), ("VGF2P8AFFINEQB", 0xce), ("VGF2P8MULB", 0xcf)
+ , ("VINSERTF128", 0x18), ("VINSERTF32X4", 0x18), ("VINSERTF32X8", 0x1a)
+ , ("VINSERTF64X2", 0x18), ("VINSERTF64X4", 0x1a), ("VINSERTI128", 0x38)
+ , ("VINSERTI32X4", 0x38), ("VINSERTI32X8", 0x3a), ("VINSERTI64X2", 0x38)
+ , ("VINSERTI64X4", 0x3a), ("VLDDQU", 0xf0), ("VMOVD", 0x6e), ("VMOVD", 0x7e)
+ , ("VMOVDDUP", 0x12), ("VMOVDQA", 0x6f), ("VMOVDQA", 0x7f)
+ , ("VMOVDQA32", 0x6f), ("VMOVDQA32", 0x7f), ("VMOVDQA64", 0x6f)
+ , ("VMOVDQA64", 0x7f), ("VMOVDQU", 0x6f), ("VMOVDQU", 0x7f)
+ , ("VMOVDQU16", 0x6f), ("VMOVDQU16", 0x7f), ("VMOVDQU32", 0x6f)
+ , ("VMOVDQU32", 0x7f), ("VMOVDQU64", 0x6f), ("VMOVDQU64", 0x7f)
+ , ("VMOVDQU8", 0x6f), ("VMOVDQU8", 0x7f), ("VMOVNTDQ", 0xe7)
+ , ("VMOVNTDQA", 0x2a), ("VMOVQ", 0x6e), ("VMOVQ", 0x7e), ("VMOVQ", 0xd6)
+ , ("VMOVSD", 0x10), ("VMOVSD", 0x11), ("VMOVSHDUP", 0x16)
+ , ("VMOVSLDUP", 0x12), ("VMPSADBW", 0x42), ("VPABSB", 0x1c), ("VPABSD", 0x1e)
+ , ("VPABSQ", 0x1f), ("VPABSW", 0x1d), ("VPACKSSDW", 0x6b)
+ , ("VPACKSSWB", 0x63), ("VPACKUSDW", 0x2b), ("VPACKUSWB", 0x67)
+ , ("VPADDB", 0xfc), ("VPADDD", 0xfe), ("VPADDQ", 0xd4), ("VPADDSB", 0xec)
+ , ("VPADDSW", 0xed), ("VPADDUSB", 0xdc), ("VPADDUSW", 0xdd), ("VPADDW", 0xfd)
+ , ("VPALIGNR", 0x0f), ("VPAND", 0xdb), ("VPANDD", 0xdb), ("VPANDN", 0xdf)
+ , ("VPANDND", 0xdf), ("VPANDNQ", 0xdf), ("VPANDQ", 0xdb), ("VPAVGB", 0xe0)
+ , ("VPAVGW", 0xe3), ("VPBLENDD", 0x02), ("VPBLENDMB", 0x66)
+ , ("VPBLENDMD", 0x64), ("VPBLENDMQ", 0x64), ("VPBLENDMW", 0x66)
+ , ("VPBLENDVB", 0x4c), ("VPBLENDW", 0x0e), ("VPBROADCASTB", 0x78)
+ , ("VPBROADCASTB", 0x7a), ("VPBROADCASTD", 0x58), ("VPBROADCASTD", 0x7c)
+ , ("VPBROADCASTMB2Q", 0x2a), ("VPBROADCASTMW2D", 0x3a)
+ , ("VPBROADCASTQ", 0x59), ("VPBROADCASTQ", 0x7c), ("VPBROADCASTW", 0x79)
+ , ("VPBROADCASTW", 0x7b), ("VPCLMULQDQ", 0x44), ("VPCMPB", 0x3f)
+ , ("VPCMPEQB", 0x74), ("VPCMPEQD", 0x76), ("VPCMPEQQ", 0x29)
+ , ("VPCMPEQW", 0x75), ("VPCMPGTB", 0x64), ("VPCMPGTD", 0x66)
+ , ("VPCMPGTQ", 0x37), ("VPCMPGTW", 0x65), ("VPCMPQ", 0x1f), ("VPCMPUB", 0x3e)
+ , ("VPCMPUD", 0x1e), ("VPCMPUQ", 0x1e), ("VPCMPUW", 0x3e), ("VPCMPW", 0x3f)
+ , ("VPERM2F128", 0x06), ("VPERM2I128", 0x46), ("VPERMD", 0x36)
+ , ("VPERMI2D", 0x76), ("VPERMI2PD", 0x77), ("VPERMI2PS", 0x77)
+ , ("VPERMI2Q", 0x76), ("VPERMI2W", 0x75), ("VPERMILPD", 0x05)
+ , ("VPERMILPD", 0x0d), ("VPERMILPS", 0x04), ("VPERMILPS", 0x0c)
+ , ("VPERMPD", 0x01), ("VPERMPD", 0x16), ("VPERMPS", 0x16), ("VPERMQ", 0x00)
+ , ("VPERMQ", 0x36), ("VPERMT2D", 0x7e), ("VPERMT2PD", 0x7f)
+ , ("VPERMT2PS", 0x7f), ("VPERMT2Q", 0x7e), ("VPERMT2W", 0x7d)
+ , ("VPERMW", 0x8d), ("VPEXTRB", 0x14), ("VPEXTRD", 0x16), ("VPEXTRQ", 0x16)
+ , ("VPEXTRW", 0x15), ("VPEXTRW", 0xc5), ("VPHADDD", 0x02), ("VPHADDSW", 0x03)
+ , ("VPHADDW", 0x01), ("VPHMINPOSUW", 0x41), ("VPHSUBD", 0x06)
+ , ("VPHSUBSW", 0x07), ("VPHSUBW", 0x05), ("VPINSRB", 0x20), ("VPINSRD", 0x22)
+ , ("VPINSRQ", 0x22), ("VPINSRW", 0xc4), ("VPLZCNTD", 0x44)
+ , ("VPLZCNTQ", 0x44), ("VPMADD52HUQ", 0xb5), ("VPMADD52LUQ", 0xb4)
+ , ("VPMADDUBSW", 0x04), ("VPMADDWD", 0xf5), ("VPMAXSB", 0x3c)
+ , ("VPMAXSQ", 0x3d), ("VPMAXSW", 0xee), ("VPMAXUB", 0xde), ("VPMAXUD", 0x3f)
+ , ("VPMAXUQ", 0x3f), ("VPMAXUW", 0x3e), ("VPMINSB", 0x38), ("VPMINSQ", 0x39)
+ , ("VPMINSW", 0xea), ("VPMINUB", 0xda), ("VPMINUD", 0x3b), ("VPMINUQ", 0x3b)
+ , ("VPMINUW", 0x3a), ("VPMOVB2M", 0x29), ("VPMOVD2M", 0x39)
+ , ("VPMOVDB", 0x31), ("VPMOVDW", 0x33), ("VPMOVM2B", 0x28)
+ , ("VPMOVM2D", 0x38), ("VPMOVM2Q", 0x38), ("VPMOVM2W", 0x28)
+ , ("VPMOVMSKB", 0xd7), ("VPMOVQ2M", 0x39), ("VPMOVQB", 0x32)
+ , ("VPMOVQD", 0x35), ("VPMOVQW", 0x34), ("VPMOVSDB", 0x21)
+ , ("VPMOVSDW", 0x23), ("VPMOVSQB", 0x22), ("VPMOVSQD", 0x25)
+ , ("VPMOVSQW", 0x24), ("VPMOVSWB", 0x20), ("VPMOVSXBD", 0x21)
+ , ("VPMOVSXBQ", 0x22), ("VPMOVSXBW", 0x20), ("VPMOVSXDQ", 0x25)
+ , ("VPMOVSXWD", 0x23), ("VPMOVSXWQ", 0x24), ("VPMOVUSDB", 0x11)
+ , ("VPMOVUSDW", 0x13), ("VPMOVUSQB", 0x12), ("VPMOVUSQD", 0x15)
+ , ("VPMOVUSQW", 0x14), ("VPMOVUSWB", 0x10), ("VPMOVW2M", 0x29)
+ , ("VPMOVWB", 0x30), ("VPMOVZXBD", 0x31), ("VPMOVZXBQ", 0x32)
+ , ("VPMOVZXBW", 0x30), ("VPMOVZXDQ", 0x35), ("VPMOVZXWD", 0x33)
+ , ("VPMOVZXWQ", 0x34), ("VPMULDQ", 0x28), ("VPMULHRSW", 0x0b)
+ , ("VPMULHUW", 0xe4), ("VPMULHW", 0xe5), ("VPMULLD", 0x40), ("VPMULLQ", 0x40)
+ , ("VPMULLW", 0xd5), ("VPMULUDQ", 0xf4), ("VPOR", 0xeb), ("VPORD", 0xeb)
+ , ("VPORQ", 0xeb), ("VPROLD", 0x72), ("VPROLQ", 0x72), ("VPROLVD", 0x15)
+ , ("VPROLVQ", 0x15), ("VPRORD", 0x72), ("VPRORQ", 0x72), ("VPRORVD", 0x14)
+ , ("VPRORVQ", 0x14), ("VPSADBW", 0xf6), ("VPSHLDD", 0x71), ("VPSHLDQ", 0x71)
+ , ("VPSHLDVD", 0x71), ("VPSHLDVQ", 0x71), ("VPSHLDVW", 0x70)
+ , ("VPSHLDW", 0x70), ("VPSHRDD", 0x73), ("VPSHRDQ", 0x73), ("VPSHRDVD", 0x73)
+ , ("VPSHRDVQ", 0x73), ("VPSHRDVW", 0x72), ("VPSHRDW", 0x72)
+ , ("VPSHUFB", 0x00), ("VPSHUFD", 0x70), ("VPSHUFHW", 0x70)
+ , ("VPSHUFLW", 0x70), ("VPSIGNB", 0x08), ("VPSIGND", 0x0a), ("VPSIGNW", 0x09)
+ , ("VPSLLD", 0x72), ("VPSLLD", 0xf2), ("VPSLLDQ", 0x73), ("VPSLLQ", 0x73)
+ , ("VPSLLQ", 0xf3), ("VPSLLVD", 0x47), ("VPSLLVQ", 0x47), ("VPSLLVW", 0x12)
+ , ("VPSLLW", 0x71), ("VPSLLW", 0xf1), ("VPSRAD", 0x72), ("VPSRAD", 0xe2)
+ , ("VPSRAQ", 0x72), ("VPSRAQ", 0xe2), ("VPSRAVD", 0x46), ("VPSRAVQ", 0x46)
+ , ("VPSRAVW", 0x11), ("VPSRAW", 0x71), ("VPSRAW", 0xe1), ("VPSRLD", 0x72)
+ , ("VPSRLD", 0xd2), ("VPSRLDQ", 0x73), ("VPSRLQ", 0x73), ("VPSRLQ", 0xd3)
+ , ("VPSRLVD", 0x45), ("VPSRLVQ", 0x45), ("VPSRLVW", 0x10), ("VPSRLW", 0x71)
+ , ("VPSRLW", 0xd1), ("VPSUBB", 0xf8), ("VPSUBD", 0xfa), ("VPSUBQ", 0xfb)
+ , ("VPSUBSB", 0xe8), ("VPSUBSW", 0xe9), ("VPSUBUSB", 0xd8)
+ , ("VPSUBUSW", 0xd9), ("VPSUBW", 0xf9), ("VPTERNLOGD", 0x25)
+ , ("VPTERNLOGQ", 0x25), ("VPTEST", 0x17), ("VPTESTMB", 0x26)
+ , ("VPTESTMD", 0x27), ("VPTESTMQ", 0x27), ("VPTESTMW", 0x26)
+ , ("VPTESTNMB", 0x26), ("VPTESTNMD", 0x27), ("VPTESTNMQ", 0x27)
+ , ("VPTESTNMW", 0x26), ("VPUNPCKHBW", 0x68), ("VPUNPCKHDQ", 0x6a)
+ , ("VPUNPCKHQDQ", 0x6d), ("VPUNPCKHWD", 0x69), ("VPUNPCKLBW", 0x60)
+ , ("VPUNPCKLDQ", 0x62), ("VPUNPCKLQDQ", 0x6c), ("VPUNPCKLWD", 0x61)
+ , ("VPXOR", 0xef), ("VPXORD", 0xef), ("VPXORQ", 0xef), ("VSHUFF32X4", 0x23)
+ , ("VSHUFF64X2", 0x23), ("VSHUFI32X4", 0x43), ("VSHUFI64X2", 0x43)
+ , ("VZEROALL", 0x77), ("VZEROUPPER", 0x77), ("XOR", 0x30), ("XOR", 0x31)
+ , ("XOR", 0x32), ("XOR", 0x33), ("XOR", 0x34), ("XOR", 0x35), ("XOR", 0x80)
+ , ("XOR", 0x81), ("XOR", 0x82), ("XOR", 0x83), ("XORPS", 0x57)
+ ]
diff --git a/lib/Vestigia/Contract/Types.hs b/lib/Vestigia/Contract/Types.hs
@@ -0,0 +1,57 @@
+{-# OPTIONS_HADDOCK prune #-}
+
+-- |
+-- Module: Vestigia.Contract.Types
+-- Copyright: (c) 2026 Jared Tobin
+-- License: MIT
+-- Maintainer: Jared Tobin <jared@ppad.tech>
+--
+-- What a contract's table says of an AArch64 encoding.
+
+module Vestigia.Contract.Types (
+ Operand(..)
+ , Status(..)
+ , Encoding(..)
+ ) where
+
+import qualified Data.Text as T
+import Data.Word (Word32)
+
+-- | A source register an encoding names, by the field it is read
+-- from: a general-purpose register at 64 or 32 bits (field value
+-- 31 the zero register, or the stack pointer where the encoding
+-- says so), a SIMD&FP register at a fixed width, a vector whose
+-- width is the encoding's Q bit (bit 30), or a SIMD&FP register
+-- read whole where nothing fixes its width.
+data Operand =
+ OpX
+ | OpXSp
+ | OpW
+ | OpWSp
+ | OpQ
+ | OpD
+ | OpS
+ | OpH
+ | OpB
+ | OpV
+ | OpVWhole
+ deriving (Eq, Show)
+
+-- | An encoding the contract covers; one it does not that is control
+-- flow or system, which reads no data the contract speaks to; or one
+-- it does not, with its source registers, each by the low bit of its
+-- field.
+data Status =
+ Covered
+ | Control
+ | Outside ![(Int, Operand)]
+ deriving (Eq, Show)
+
+-- | An encoding, by its name in the specification, its fixed bits,
+-- and what the contract says of it.
+data Encoding = Encoding {
+ enName :: !T.Text
+ , enMask :: !Word32
+ , enValue :: !Word32
+ , enStatus :: !Status
+ } deriving (Eq, Show)
diff --git a/lib/Vestigia/Diff.hs b/lib/Vestigia/Diff.hs
@@ -63,6 +63,13 @@
-- runs that never reached it. Whether two runs
-- that differed there both had their secrets accepted is the
-- reader's to say, from what each run returned.
+--
+-- Runs recorded under a data-independent-timing contract
+-- (Vestigia.Contract) also fingerprint the operands of every
+-- instruction outside it. One run equally often on other operands
+-- in some declared run is outside the contract on the secret: not an
+-- origin, since the contract says nothing either way of its time,
+-- but reported beside them, as is how many such instructions ran.
module Vestigia.Diff (
Insn(..)
@@ -96,6 +103,7 @@ import qualified Data.Text.Encoding.Error as TEE
import Numeric (readHex, showHex)
import Text.Read (readMaybe)
+import Vestigia.Contract (contractSource, readContract)
import Vestigia.Json
import Vestigia.Symbol (Place(..))
@@ -137,6 +145,15 @@ data Dump = Dump {
, dpContexts :: !(M.Map Integer (Integer, Integer))
, dpCallers :: !(M.Map Integer (Bool, [Integer]))
, dpRun :: !(Maybe Run)
+ -- | the operands, fingerprinted, of the instructions outside the
+ -- contract the run was recorded under
+ , dpOutside :: !(M.Map Integer T.Text)
+ -- | the text of each instruction the watch list named
+ , dpTexts :: !(M.Map Integer T.Text)
+ -- | the guest's ISA, and the contract, as `vestigia record`
+ -- appends them
+ , dpIsa :: !(Maybe T.Text)
+ , dpContract :: !(Maybe T.Text)
} deriving (Eq, Show)
-- | Read a plugin dump. A dump in which no instruction ran records
@@ -147,11 +164,13 @@ data Dump = Dump {
-- program's own. The record `vestigia record` appends (an @A@ line
-- per argument, its bytes in hex; @N@, the environment's variables
-- and bytes, in hex; @X@, the exit status, in decimal) is read
--- whole or not at all.
+-- whole or not at all. Beside it, @M@ names the guest's ISA and @G@
+-- the contract the run was recorded under.
readDump :: T.Text -> Either String Dump
readDump t = do
d <- foldM line (Dump M.empty M.empty S.empty M.empty M.empty M.empty
- Nothing, [], Nothing, Nothing) (T.lines t)
+ Nothing M.empty M.empty Nothing Nothing, [], Nothing
+ , Nothing) (T.lines t)
let (dump, as, env, st) = d
cx = dpContexts dump
unless (any ((> 0) . inCount) (M.elems (dpInsns dump))) $
@@ -187,6 +206,16 @@ readDump t = do
k <- unhex pc
pure (d { dpOperands = M.insert k fp (dpOperands d) }, as, env
, st)
+ [ "U", pc, fp ] -> do
+ k <- unhex pc
+ pure (d { dpOutside = M.insert k fp (dpOutside d) }, as, env
+ , st)
+ ("W" : pc : text@(_ : _)) -> do
+ k <- unhex pc
+ pure (d { dpTexts = M.insert k (T.unwords text) (dpTexts d) }, as
+ , env, st)
+ [ "M", isa ] -> pure (d { dpIsa = Just isa }, as, env, st)
+ [ "G", c ] -> pure (d { dpContract = Just c }, as, env, st)
[ "C", c, caller, call ] -> do
v <- (,) <$> unhex caller <*> unhex call
k <- unhex c
@@ -324,6 +353,20 @@ data Divergence = Divergence {
-- in the declared and designed runs, at most 16 of them, and
-- whether there were more than those
, dvCallers :: !(M.Map Integer ([[(Maybe T.Text, Integer)]], Bool))
+ -- | the instructions outside the contract run equally often in
+ -- every declared run, on other operands in one, each with the
+ -- runs alike there and those that never ran it
+ , dvOutside :: ![Insn]
+ , dvOutsideBehaviour :: !(M.Map Integer ([[Int]], [Int]))
+ -- | the instructions outside the contract some run executed, by
+ -- object
+ , dvWatched :: !(M.Map T.Text (S.Set Integer))
+ -- | the text of each instruction the watch list named
+ , dvTexts :: !(M.Map Integer T.Text)
+ -- | the guest's ISA and the contract, as the declared runs name
+ -- them
+ , dvIsa :: !(Maybe T.Text)
+ , dvContract :: !(Maybe T.Text)
} deriving (Eq, Show)
-- | Compare runs, uncontrolled.
@@ -361,9 +404,36 @@ diffDesigned cs ds xs = Divergence {
, inCount i > 0
, Just obj <- [ inObject i ] ]
, dvCallers = M.fromList
- [ (inPc i, callersAt (inPc i)) | (_, i) <- origins ]
+ [ (inPc i, callersAt (inPc i))
+ | i <- fmap snd origins <> outside ]
+ , dvOutside = outside
+ , dvOutsideBehaviour = M.fromList
+ [ ( inPc i
+ , ( classes (==) [ (k, M.lookup (inPc i) (dpOutside d))
+ | (k, d) <- ranIn' ds (inPc i) ]
+ , [ k | (k, d) <- zip [ 0 .. ] ds
+ , maybe True ((== 0) . inCount)
+ (M.lookup (inPc i) (dpInsns d)) ] ) )
+ | i <- outside ]
+ , dvWatched = M.fromListWith S.union
+ [ (obj, S.singleton (inOffset i))
+ | d <- ds <> xs <> cs
+ , pc <- M.keys (dpOutside d)
+ , Just i <- [ M.lookup pc (dpInsns d) ]
+ , inCount i > 0
+ , Just obj <- [ inObject i ] ]
+ , dvTexts = M.unions (fmap dpTexts (ds <> xs <> cs))
+ , dvIsa = case ds of
+ (d : _) -> dpIsa d
+ [] -> Nothing
+ , dvContract = case ds of
+ (d : _) -> dpContract d
+ [] -> Nothing
}
where
+ ranIn' rs pc = [ (k, d) | (k, d) <- zip [ 0 .. ] rs
+ , Just i <- [ M.lookup pc (dpInsns d) ]
+ , inCount i > 0 ]
callersAt pc =
let found = [ (partial, fmap (callsOf d) ks)
| d <- runs
@@ -384,7 +454,8 @@ diffDesigned cs ds xs = Divergence {
ta = M.lookup pc (dpTransfers a)
tb = M.lookup pc (dpTransfers b)
, fmap sig ia /= fmap sig ib || ta /= tb
- || M.lookup pc (dpOperands a) /= M.lookup pc (dpOperands b) ]
+ || M.lookup pc (dpOperands a) /= M.lookup pc (dpOperands b)
+ || M.lookup pc (dpOutside a) /= M.lookup pc (dpOutside b) ]
sig i = (inCount i, inFingerprint i, inOrder i)
origins = [ o | o@(_, i) <- controls <> addresses <> operands
@@ -467,10 +538,11 @@ diffDesigned cs ds xs = Divergence {
-- the address and operand origins
dataPcs = S.fromList [ inPc i | (_, i) <- addresses <> operands ]
downstream =
- (((pcs `S.difference` steady)
- `S.union` (divergentPcs `S.intersection` returns))
- `S.difference` controlPcs)
- `S.difference` dataPcs
+ ((((pcs `S.difference` steady)
+ `S.union` (divergentPcs `S.intersection` returns))
+ `S.difference` controlPcs)
+ `S.difference` dataPcs)
+ `S.difference` S.fromList (fmap inPc outside)
controls =
[ (ControlOrigin, i)
@@ -486,6 +558,20 @@ diffDesigned cs ds xs = Divergence {
, Just i <- [ firstInsn pc ]
, inAccesses i > 0 ]
+ -- an instruction outside the contract run equally often in
+ -- every declared run, on other operands in one, where it is not
+ -- an origin already
+ outside =
+ [ i
+ | pc <- S.toAscList steadyDeclared
+ , not (pc `S.member` unsteady)
+ , not (pc `S.member` controlPcs)
+ , not (pc `S.member` dataPcs)
+ , let fps = [ M.lookup pc (dpOutside d) | d <- ds ]
+ , any (/= Nothing) fps
+ , not (alike fps)
+ , Just i <- [ firstInsn pc ] ]
+
-- a division run equally often in every declared run, on other
-- operands in one
operands =
@@ -506,6 +592,9 @@ restrictTo ps dv
, dvDownstream = filter (inside . inObject) (dvDownstream dv)
, dvExecuted = M.filterWithKey (\o _ -> inside (Just o))
(dvExecuted dv)
+ , dvOutside = filter (inside . inObject) (dvOutside dv)
+ , dvWatched = M.filterWithKey (\o _ -> inside (Just o))
+ (dvWatched dv)
}
where
inside mo = case mo of
@@ -518,19 +607,29 @@ originText o = case o of
AddressOrigin -> "address"
OperandOrigin -> "operand"
--- | The report: @vestigia/diff-v3@. Runs are given the declared,
+-- | The report: @vestigia/diff-v4@. Runs are given the declared,
-- then the designed, then the controls, and an origin names the
-- runs alike at it by the first two. An origin's stacks are its own
-- frames then its calls', innermost first, each frame with the
-- object and address of the instruction it names, as memcheck's
--- are in a taint report.
+-- are in a taint report. The ISA and contract the runs were
+-- recorded under head it; the instructions outside the contract
+-- whose operands differed are given as origins are, and those that
+-- ran, by object, as what was executed is.
divergenceJson
:: T.Text -> [Named] -> M.Map (T.Text, Integer) [Place] -> Divergence
-> Value
divergenceJson version runs places dv = Object
- [ ("schema", String "vestigia/diff-v3")
+ [ ("schema", String "vestigia/diff-v4")
, ("tool", Object [ ("name", String "vestigia")
, ("version", String version) ])
+ , ("isa", maybe Null String (dvIsa dv))
+ , ("contract", case dvContract dv of
+ Just n -> Object
+ [ ("name", String n)
+ , ("source", maybe Null (String . contractSource)
+ (readContract n)) ]
+ Nothing -> Null)
, ("runs", Array
[ Object
[ ("name", String (nmName r))
@@ -547,28 +646,18 @@ divergenceJson version runs places dv = Object
, ("operand", count OperandOrigin)
, ("downstream", Number (toInteger (length (dvDownstream dv))))
, ("unsteady", Number (toInteger (length (dvUnsteady dv))))
+ , ("outside", Number (toInteger (length (dvOutside dv))))
+ , ("watched", Number (toInteger (sum (fmap S.size
+ (M.elems (dvWatched dv))))))
])
, ("origins", Array
- [ Object $
- [ ("class", String (originText o))
- , ("pc", String (hex (inPc i)))
- , ("object", maybe Null String (inObject i))
- , ("offset", String (hex (inOffset i)))
- , ("count", Number (inCount i))
- , ("frames", Array (fmap placeJson (placesOf i)))
- , ("stacks", Array
- [ Array (located (inObject i, inOffset i)
- <> concatMap located calls)
- | calls <- stacks ])
- , ("partial", Bool partial)
- , ("groups", Array (fmap (Array . fmap named) groups))
- , ("absent", Array (fmap named absent))
- ]
- | (o, i) <- dvOrigins dv
- , let (groups, absent) = M.findWithDefault ([], []) (o, inPc i)
- (dvBehaviour dv)
- (stacks, partial) = M.findWithDefault ([], False) (inPc i)
- (dvCallers dv) ])
+ [ site (originText o) i
+ (M.findWithDefault ([], []) (o, inPc i) (dvBehaviour dv))
+ | (o, i) <- dvOrigins dv ])
+ , ("outside", Array
+ [ site "outside" i
+ (M.findWithDefault ([], []) (inPc i) (dvOutsideBehaviour dv))
+ | i <- dvOutside dv ])
, ("downstream", Object
[ (obj, Array (fmap (String . hex) (S.toAscList offs)))
| (obj, offs) <- M.toList (M.fromListWith S.union
@@ -578,8 +667,31 @@ divergenceJson version runs places dv = Object
, ("executed", Object
[ (o, Array (fmap (String . hex) (S.toAscList xs)))
| (o, xs) <- M.toList (dvExecuted dv) ])
+ , ("watched", Object
+ [ (o, Array (fmap (String . hex) (S.toAscList xs)))
+ | (o, xs) <- M.toList (dvWatched dv) ])
]
where
+ site cls i (groups, absent) =
+ let (stacks, partial) = M.findWithDefault ([], False) (inPc i)
+ (dvCallers dv)
+ in Object
+ [ ("class", String cls)
+ , ("pc", String (hex (inPc i)))
+ , ("object", maybe Null String (inObject i))
+ , ("offset", String (hex (inOffset i)))
+ , ("count", Number (inCount i))
+ , ("instruction", maybe Null String
+ (M.lookup (inPc i) (dvTexts dv)))
+ , ("frames", Array (fmap placeJson (placesOf i)))
+ , ("stacks", Array
+ [ Array (located (inObject i, inOffset i)
+ <> concatMap located calls)
+ | calls <- stacks ])
+ , ("partial", Bool partial)
+ , ("groups", Array (fmap (Array . fmap named) groups))
+ , ("absent", Array (fmap named absent))
+ ]
names = [ nmName r | r <- runs, nmKind r /= ControlRun ]
kindText k = case k of
DeclaredRun -> "declared"
@@ -623,12 +735,13 @@ divergenceSummary
:: M.Map (T.Text, Integer) [Place] -> Divergence -> T.Text
divergenceSummary places dv = T.unlines $
[ T.intercalate " "
- [ originText o
+ [ cls
, hex (inOffset i)
, maybe "?" id (plFunction =<< innermost i)
, maybe "?" location (innermost i)
, maybe "-" base (inObject i) ]
- | (o, i) <- dvOrigins dv ]
+ | (cls, i) <- [ (originText o, i) | (o, i) <- dvOrigins dv ]
+ <> [ ("outside", i) | i <- dvOutside dv ] ]
<> [ T.pack (show (length (dvOrigins dv))) <> " origin(s) over "
<> T.pack (show (dvRuns dv)) <> " run(s)"
<> (if dvDesigned dv == 0 then ""
@@ -638,8 +751,15 @@ divergenceSummary places dv = T.unlines $
<> " instruction(s) downstream; "
<> T.pack (show (length (dvUnsteady dv)))
<> " unsteady over " <> T.pack (show (dvControls dv))
- <> " control(s)" ]
+ <> " control(s)"
+ <> maybe ""
+ (\c -> "; " <> T.pack (show watched)
+ <> " instruction(s) outside " <> c <> " ran, "
+ <> T.pack (show (length (dvOutside dv)))
+ <> " on operands that differed")
+ (dvContract dv) ]
where
+ watched = sum (fmap S.size (M.elems (dvWatched dv)))
innermost i = case inObject i of
Just obj -> case M.findWithDefault [] (obj, inOffset i) places of
(p : _) -> Just p
diff --git a/nix/lib.nix b/nix/lib.nix
@@ -67,6 +67,8 @@ let
"${plugin}/lib/libvestigia-qemu.so"
"--set-default VESTIGIA_ADDR2LINE"
"${pkgs.llvm}/bin/llvm-addr2line"
+ "--set-default VESTIGIA_OBJDUMP"
+ "${pkgs.llvm}/bin/llvm-objdump"
])}
ln -s ${include}/include $out/include
'';
@@ -111,16 +113,26 @@ let
# without the secret is set aside rather than taken for it.
# `designed` runs, aimed at particular paths, are compared beside
# them for control and coverage but not for addresses (vestigia
- # diff --designed). A run's own failure leaves its status; a dump
- # vestigia cannot read fails the build.
- diffOf = { name, harness, runs, objects ? [ ], designed ? [ ] }:
+ # diff --designed). Under a `contract` (arm-dit or intel-doitm, the
+ # harness's ISA's), every run also fingerprints the operands of the
+ # instructions outside it in `objects` (vestigia record --contract).
+ # A run's own failure leaves its status; a dump vestigia cannot read
+ # fails the build.
+ diffOf = { name, harness, runs, objects ? [ ], designed ? [ ]
+ , contract ? null }:
+ let
+ watch = lib.optionalString (contract != null)
+ ("--contract ${lib.escapeShellArg contract} "
+ + lib.concatMapStrings (o: "--object ${lib.escapeShellArg o} ")
+ objects);
+ in
pkgs.runCommand "vestigia-diff-${name}" { } ''
mkdir -p $out
start=$(date +%s%N)
${lib.concatImapStrings (k: args: ''
set +e
${vestigia}/bin/vestigia record --dump $out/dump-${toString k} \
- -- ${harness} ${lib.escapeShellArgs args} \
+ ${watch}-- ${harness} ${lib.escapeShellArgs args} \
> $out/stdout-${toString k} 2> $out/stderr-${toString k}
echo $? > $out/status-${toString k}
set -e
@@ -128,7 +140,7 @@ let
set +e
${vestigia}/bin/vestigia record \
--dump $out/designed-${toString k} \
- -- ${harness} ${lib.escapeShellArgs args} \
+ ${watch}-- ${harness} ${lib.escapeShellArgs args} \
> $out/stdout-designed-${toString k} \
2> $out/stderr-designed-${toString k}
echo $? > $out/status-designed-${toString k}
@@ -136,7 +148,7 @@ let
'') designed}
set +e
${vestigia}/bin/vestigia record --dump $out/control-1 \
- -- ${harness} ${lib.escapeShellArgs (builtins.head runs)} \
+ ${watch}-- ${harness} ${lib.escapeShellArgs (builtins.head runs)} \
> $out/stdout-control-1 2> $out/stderr-control-1
echo $? > $out/status-control-1
set -e
diff --git a/nix/probe.nix b/nix/probe.nix
@@ -2,7 +2,9 @@
# site and origin it should show found where it should be, and
# nothing else in the harness. On an x86_64 host, the same harness
# built for aarch64 is traced differentially too, under QEMU; memcheck
-# needs a native host.
+# needs a native host. Each differential trace is repeated under its
+# ISA's data-independent-timing contract, which finds the floating-
+# point division outside it and changes no origin.
{ pkgs, vestigia }:
let
@@ -41,13 +43,16 @@ let
inherit objects;
};
- diffOf = name: harness: vestigia.diffOf {
- inherit name objects;
+ diffOf = name: harness: contract: vestigia.diffOf {
+ inherit name objects contract;
harness = "${harness}/bin/probe";
runs = map (s: [ s ]) secrets;
};
- diff = diffOf "probe" probe;
- diffCross = diffOf "probe-aarch64" cross;
+ native = if x86_64 then "intel-doitm" else "arm-dit";
+ diff = diffOf "probe" probe null;
+ diffCross = diffOf "probe-aarch64" cross null;
+ diffContract = diffOf "probe-contract" probe native;
+ diffCrossContract = diffOf "probe-aarch64-contract" cross "arm-dit";
# each report's (class, function) pairs in the harness, sorted
expected = {
@@ -98,6 +103,27 @@ pkgs.runCommand "vestigia-probe-check" {
'${builtins.toJSON expected.diff}'
''}
+ # under a contract, the floating-point division is outside it, and
+ # the origins are those found without one
+ for d in ${diffContract} ${lib.optionalString x86_64
+ "${diffCrossContract}"}; do
+ check $d/diff.json '[.outside[] | .frames[0].function] | unique' \
+ '["fpdivide"]'
+ check $d/diff.json \
+ '[.origins[] | [.class, .frames[0].function]] | unique' \
+ '${builtins.toJSON expected.diff}'
+ check $d/diff.json '.summary.watched > 0' 'true'
+ check $d/diff.json '[.outside[] | .instruction | type] | unique' \
+ '["string"]'
+ done
+ check ${diffContract}/diff.json '[.contract.name, .isa]' \
+ '${builtins.toJSON [ native (if x86_64 then "x86_64" else "aarch64") ]}'
+ check ${diff}/diff.json '.contract' 'null'
+ ${lib.optionalString x86_64 ''
+ check ${diffCrossContract}/diff.json '[.contract.name, .isa]' \
+ '["arm-dit","aarch64"]'
+ ''}
+
# each origin's stack runs from its own function to the call in
# main that reached it
for d in ${diff} ${lib.optionalString x86_64 "${diffCross}"}; do
diff --git a/plugin/vestigia-qemu.c b/plugin/vestigia-qemu.c
@@ -31,12 +31,32 @@
* division) is given the contexts it ran in: the chains of calls, by
* their addresses, that reached it, up to CONTEXTS of them.
*
+ * Given a watch list (its `watch` argument, written by `vestigia
+ * record` under a data-independent-timing contract), it also
+ * fingerprints the operands of every instruction the list names: each
+ * one outside the contract, by its object and address there, with the
+ * registers it reads, fingerprinted before it runs, and any value it
+ * loads or stores, as it is accessed. One run as often but on other
+ * operands computed them from the secret. The list names divisions
+ * too, for their text alone: the plugin reads a division's operands
+ * from its bytes, as above. A list is read whole:
+ *
+ * O <object>
+ * D <address> <text>
+ * U <address> <memory> <n> <register>:<low>:<width>... <text>
+ *
+ * in hex where an address, each register by the name QEMU's debugger
+ * stub gives it, the bits read from its low bit; <memory> is 1 where
+ * the instruction names memory.
+ *
* At exit it writes, to the file named by its `out` argument:
*
* I <pc> <count> <accesses> <fingerprint> <order> <object> <address>
* E <from> <to> <count>
* R <pc>
* D <pc> <operands>
+ * U <pc> <operands>
+ * W <pc> <text>
* C <context> <caller> <call>
* K <pc> <partial> <context>...
*
@@ -67,8 +87,9 @@
QEMU_PLUGIN_EXPORT int qemu_plugin_version = QEMU_PLUGIN_VERSION;
-/* what an instruction is to a comparison, read from its bytes */
-enum { PLAIN, RETURN, DIVISION, CALL };
+/* what an instruction is to a comparison, read from its bytes, or
+ from the watch list (OUTSIDE) */
+enum { PLAIN, RETURN, DIVISION, CALL, OUTSIDE };
/* the most contexts kept for one instruction */
#define CONTEXTS 16
@@ -85,6 +106,16 @@ typedef struct Decoded {
int width, a, b, high;
} Decoded;
+/* an instruction the watch list names */
+typedef struct Watch {
+ int division; /* a division, named for its text alone */
+ int nregs;
+ char **names; /* the registers it reads, by QEMU's names */
+ int *low, *width; /* the bits read of each */
+ struct qemu_plugin_register **handles;
+ char *text;
+} Watch;
+
typedef struct Insn {
uint64_t pc;
uint64_t size;
@@ -94,7 +125,9 @@ typedef struct Insn {
uint64_t accesses;
uint64_t fingerprint;
uint64_t order; /* the successors, in the order they followed */
- uint64_t operands; /* a division's operands, in order */
+ uint64_t operands; /* a division's or a watched instruction's
+ operands, in order */
+ const Watch *watch; /* where the watch list names it */
GHashTable *succ; /* target pc -> count, for transfers */
uint32_t last; /* the context it last ran in */
uint32_t contexts[CONTEXTS];
@@ -127,6 +160,10 @@ static GArray *calls; /* the calls in progress, innermost last */
static uint32_t current; /* the context the guest runs in */
static struct qemu_plugin_register *gpr[GPRS];
static GByteArray *regbuf;
+static GHashTable *watches; /* "<object>\n<address>" -> Watch */
+static GHashTable *registers; /* QEMU's name -> its handle */
+static GArray *regions; /* the host's mappings, as last read */
+static GHashTable *segments; /* a file's path -> its Segments */
static const uint64_t fnv_offset = 0xcbf29ce484222325ULL;
static const uint64_t fnv_prime = 0x100000001b3ULL;
@@ -334,6 +371,25 @@ static void on_divide(unsigned int vcpu, void *udata) {
mix(i, (read_gpr(i->d.a) >> (i->d.high ? 8 : 0)) & mask);
}
+/* a watched instruction: each register it reads, its bits from the
+ low one, mixed in eight bytes at a time */
+static void on_outside(unsigned int vcpu, void *udata) {
+ Insn *i = udata;
+ const Watch *w = i->watch;
+ (void)vcpu;
+ for (int k = 0; k < w->nregs; k++) {
+ int n, from = w->low[k] / 8, to = (w->low[k] + w->width[k]) / 8;
+ g_byte_array_set_size(regbuf, 0);
+ n = qemu_plugin_read_register(w->handles[k], regbuf);
+ if (to > n) to = n;
+ for (int b = from; b < to; b += 8) {
+ uint64_t v = 0;
+ memcpy(&v, regbuf->data + b, MIN((size_t)(to - b), sizeof v));
+ mix(i, v);
+ }
+ }
+}
+
static void on_mem(unsigned int vcpu, qemu_plugin_meminfo_t info,
uint64_t vaddr, void *udata) {
Insn *i = udata;
@@ -341,7 +397,7 @@ static void on_mem(unsigned int vcpu, qemu_plugin_meminfo_t info,
i->fingerprint = (i->fingerprint ^ vaddr) * fnv_prime;
i->accesses++;
if (i->last != current) note_context(i);
- if (i->d.kind == DIVISION) {
+ if (i->d.kind == DIVISION || i->d.kind == OUTSIDE) {
qemu_plugin_mem_value v = qemu_plugin_mem_get_value(info);
switch (v.type) {
case QEMU_PLUGIN_MEM_VALUE_U8: mix(i, v.data.u8); break;
@@ -367,6 +423,7 @@ static void find_registers(void) {
for (guint k = 0; k < rs->len; k++) {
qemu_plugin_reg_descriptor *r =
&g_array_index(rs, qemu_plugin_reg_descriptor, k);
+ g_hash_table_insert(registers, g_strdup(r->name), r->handle);
for (int j = 0; j < wanted; j++) {
char name[8];
if (aarch64) g_snprintf(name, sizeof name, "x%d", j);
@@ -381,6 +438,28 @@ static void find_registers(void) {
"which a division's operands are read\n", j);
_exit(EXIT_FAILURE);
}
+ /* every register the watch list reads, or none of the run */
+ GHashTableIter it;
+ gpointer key, val;
+ g_hash_table_iter_init(&it, watches);
+ while (g_hash_table_iter_next(&it, &key, &val)) {
+ Watch *w = val;
+ for (int k = 0; k < w->nregs; k++) {
+ w->handles[k] = g_hash_table_lookup(registers, w->names[k]);
+ /* a CPU with SVE names its SIMD&FP registers by their scalable
+ views, whose low 128 bits they are */
+ if (w->handles[k] == NULL && w->names[k][0] == 'v') {
+ char *z = g_strdup_printf("z%s", w->names[k] + 1);
+ w->handles[k] = g_hash_table_lookup(registers, z);
+ g_free(z);
+ }
+ if (w->handles[k] == NULL) {
+ fprintf(stderr, "vestigia-qemu: QEMU names no register %s, "
+ "which the watch list reads\n", w->names[k]);
+ _exit(EXIT_FAILURE);
+ }
+ }
+ }
}
static void on_vcpu_init(qemu_plugin_id_t id, unsigned int vcpu) {
@@ -400,6 +479,8 @@ static void on_vcpu_init(qemu_plugin_id_t id, unsigned int vcpu) {
}
}
+static const Watch *watched(uintptr_t haddr);
+
static void on_translate(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) {
size_t n = qemu_plugin_tb_n_insns(tb);
(void)id;
@@ -412,12 +493,25 @@ static void on_translate(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) {
(uintptr_t)qemu_plugin_insn_haddr(qi),
aarch64 ? decode_aarch64(bytes, len)
: decode_x86_64(bytes, len));
- if (k == n - 1 || i->d.kind == DIVISION) i->origin = 1;
+ /* an instruction the watch list names: a division its text, any
+ other its registers; one translated anew keeps what it had */
+ if (i->watch == NULL && g_hash_table_size(watches) > 0) {
+ const Watch *w = watched(i->haddr);
+ if (w != NULL && (i->d.kind == DIVISION || !w->division)) {
+ i->watch = w;
+ if (i->d.kind != DIVISION) i->d.kind = OUTSIDE;
+ }
+ }
+ if (k == n - 1 || i->d.kind == DIVISION || i->d.kind == OUTSIDE)
+ i->origin = 1;
qemu_plugin_register_vcpu_insn_exec_cb(qi, on_exec,
QEMU_PLUGIN_CB_NO_REGS, i);
if (i->d.kind == DIVISION)
qemu_plugin_register_vcpu_insn_exec_cb(qi, on_divide,
QEMU_PLUGIN_CB_R_REGS, i);
+ else if (i->d.kind == OUTSIDE)
+ qemu_plugin_register_vcpu_insn_exec_cb(qi, on_outside,
+ QEMU_PLUGIN_CB_R_REGS, i);
qemu_plugin_register_vcpu_mem_cb(qi, on_mem, QEMU_PLUGIN_CB_NO_REGS,
QEMU_PLUGIN_MEM_RW, i);
}
@@ -527,6 +621,110 @@ static gboolean address_in(const Segments *s, uint64_t off,
return FALSE;
}
+/* the watch list's entry for the instruction at a host address: its
+ file and address there, the mappings read anew where the address
+ lies in none known */
+static const Watch *watched(uintptr_t haddr) {
+ const Region *r = region_of(regions, haddr);
+ Segments *s;
+ uint64_t addr;
+ if (r == NULL) {
+ for (guint k = 0; k < regions->len; k++)
+ g_free(g_array_index(regions, Region, k).path);
+ g_array_free(regions, TRUE);
+ regions = read_maps();
+ r = region_of(regions, haddr);
+ }
+ if (r == NULL) return NULL;
+ s = segments_of(segments, r->path);
+ if (s == NULL
+ || !address_in(s, (uint64_t)(haddr - r->start) + r->offset, &addr))
+ return NULL;
+ char *key = g_strdup_printf("%s\n%" PRIx64, r->path, addr);
+ const Watch *w = g_hash_table_lookup(watches, key);
+ g_free(key);
+ return w;
+}
+
+/* read a watch list whole; a line it cannot read stops the run */
+static gboolean read_watches(const char *path) {
+ gchar *text = NULL;
+ gchar *object = NULL;
+ if (!g_file_get_contents(path, &text, NULL, NULL)) {
+ fprintf(stderr, "vestigia-qemu: cannot read the watch list %s\n",
+ path);
+ return FALSE;
+ }
+ gchar **lines = g_strsplit(text, "\n", -1);
+ gboolean ok = TRUE;
+ for (gchar **l = lines; ok && *l != NULL; l++) {
+ gchar *line = *l;
+ if (line[0] == '\0') continue;
+ if (line[0] == 'O' && line[1] == ' ') {
+ g_free(object);
+ object = g_strdup(line + 2);
+ continue;
+ }
+ if (object == NULL || (line[0] != 'D' && line[0] != 'U')
+ || line[1] != ' ') {
+ ok = FALSE;
+ break;
+ }
+ char *p = line + 2, *end;
+ uint64_t addr = g_ascii_strtoull(p, &end, 16);
+ Watch *w = g_new0(Watch, 1);
+ if (end == p || *end != ' ') ok = FALSE;
+ p = end + 1;
+ if (ok && line[0] == 'D')
+ w->division = 1;
+ else if (ok) {
+ /* <memory> <n> then n registers */
+ if ((p[0] != '0' && p[0] != '1') || p[1] != ' ') ok = FALSE;
+ p += 2;
+ w->nregs = ok ? (int)g_ascii_strtoll(p, &end, 10) : 0;
+ if (end == p || *end != ' ' || w->nregs < 0 || w->nregs > 16)
+ ok = FALSE;
+ p = end + 1;
+ w->names = g_new0(char *, w->nregs);
+ w->low = g_new0(int, w->nregs);
+ w->width = g_new0(int, w->nregs);
+ w->handles = g_new0(struct qemu_plugin_register *, w->nregs);
+ for (int k = 0; ok && k < w->nregs; k++) {
+ char *sp = strchr(p, ' ');
+ if (sp == NULL) {
+ ok = FALSE;
+ break;
+ }
+ gchar *spec = g_strndup(p, (gsize)(sp - p));
+ gchar **f = g_strsplit(spec, ":", 3);
+ g_free(spec);
+ if (g_strv_length(f) != 3) ok = FALSE;
+ else {
+ w->names[k] = g_strdup(f[0]);
+ w->low[k] = atoi(f[1]);
+ w->width[k] = atoi(f[2]);
+ if (w->low[k] % 8 != 0 || w->width[k] % 8 != 0
+ || w->width[k] <= 0)
+ ok = FALSE;
+ }
+ g_strfreev(f);
+ p = sp + 1;
+ }
+ }
+ if (!ok) break;
+ w->text = g_strdup(p);
+ g_hash_table_insert(watches,
+ g_strdup_printf("%s\n%" PRIx64, object, addr), w);
+ }
+ if (!ok)
+ fprintf(stderr, "vestigia-qemu: %s: an unreadable watch list\n",
+ path);
+ g_strfreev(lines);
+ g_free(object);
+ g_free(text);
+ return ok;
+}
+
static void at_exit(qemu_plugin_id_t id, void *p) {
(void)id;
(void)p;
@@ -558,6 +756,10 @@ static void at_exit(qemu_plugin_id_t id, void *p) {
if (i->d.kind == RETURN) fprintf(out, "R %" PRIx64 "\n", i->pc);
if (i->d.kind == DIVISION)
fprintf(out, "D %" PRIx64 " %016" PRIx64 "\n", i->pc, i->operands);
+ if (i->d.kind == OUTSIDE)
+ fprintf(out, "U %" PRIx64 " %016" PRIx64 "\n", i->pc, i->operands);
+ if (i->watch != NULL)
+ fprintf(out, "W %" PRIx64 " %s\n", i->pc, i->watch->text);
if (i->ncontexts > 0) {
fprintf(out, "K %" PRIx64 " %d", i->pc, i->partial);
for (int k = 0; k < i->ncontexts; k++)
@@ -582,16 +784,25 @@ static void at_exit(qemu_plugin_id_t id, void *p) {
QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
const qemu_info_t *info,
int argc, char **argv) {
+ const char *watch_path = NULL;
aarch64 = strcmp(info->target_name, "aarch64") == 0;
for (int k = 0; k < argc; k++)
if (strncmp(argv[k], "out=", 4) == 0)
out_path = g_strdup(argv[k] + 4);
+ else if (strncmp(argv[k], "watch=", 6) == 0)
+ watch_path = argv[k] + 6;
if (out_path == NULL) {
fprintf(stderr, "vestigia-qemu: an out=FILE argument is needed\n");
return -1;
}
insns = g_hash_table_new(g_int64_hash, g_int64_equal);
regbuf = g_byte_array_new();
+ watches = g_hash_table_new(g_str_hash, g_str_equal);
+ registers = g_hash_table_new_full(g_str_hash, g_str_equal, g_free,
+ NULL);
+ regions = g_array_new(FALSE, FALSE, sizeof(Region));
+ segments = g_hash_table_new(g_str_hash, g_str_equal);
+ if (watch_path != NULL && !read_watches(watch_path)) return -1;
contexts = g_array_new(FALSE, FALSE, sizeof(Context));
interned = g_hash_table_new_full(context_hash, context_equal, g_free,
NULL);
diff --git a/test/Main.hs b/test/Main.hs
@@ -12,6 +12,7 @@ import qualified Data.Text.Encoding as TE
import Test.Tasty
import Test.Tasty.HUnit
+import Vestigia.Contract
import Vestigia.Diff
import Vestigia.Json
import Vestigia.Memcheck
@@ -24,6 +25,7 @@ main = defaultMain $ testGroup "vestigia"
[ xmlTests
, memcheckTests
, traceTests
+ , contractTests
, diffTests
, symbolTests
, jsonTests
@@ -142,6 +144,94 @@ traceTests = testGroup "trace"
fmap fst (trUnrelated tr) @?= [ 0 ]
]
+contractTests :: TestTree
+contractTests = testGroup "contract"
+ [ testCase "AArch64: a division, and what DIT covers" $ do
+ classify ArmDit (word 0x1ac20820) @?= Division -- udiv w0
+ classify ArmDit (word 0x9ac20c20) @?= Division -- sdiv x0
+ classify ArmDit (word 0x8b020020) @?= Inside -- add x0
+ classify ArmDit (word 0x9bc27c20) @?= Inside -- umulh x0
+ classify ArmDit (word 0xdac00c20) @?= Inside -- rev x0
+ classify ArmDit (word 0xd65f03c0) @?= Excluded -- ret
+ classify ArmDit (word 0x90000420) @?= Excluded -- adrp x0
+
+ , testCase "AArch64: outside DIT, with the registers read" $ do
+ -- fdiv d0, d1, d2
+ classify ArmDit (word 0x1e621820)
+ @?= Watched [ Register "v1" 0 64, Register "v2" 0 64 ] False
+ -- fmov x0, d1
+ classify ArmDit (word 0x9e660020)
+ @?= Watched [ Register "v1" 0 64 ] False
+ -- fadd v0.4s, v1.4s, v2.4s, and its 64-bit arrangement
+ classify ArmDit (word 0x4e22d420)
+ @?= Watched [ Register "v1" 0 128, Register "v2" 0 128 ] False
+ classify ArmDit (word 0x0e22d420)
+ @?= Watched [ Register "v1" 0 64, Register "v2" 0 64 ] False
+
+ , testCase "x86_64: a division, and what DOITM covers" $ do
+ classify IntelDoitm (x86 [ 0x48, 0xf7, 0xf6 ] "div" "rsi")
+ @?= Division
+ classify IntelDoitm (x86 [ 0xc1, 0xc0, 0x07 ] "rol" "eax, 0x7")
+ @?= Inside
+ classify IntelDoitm (x86 [ 0x48, 0x0f, 0xc8 ] "bswap" "rax")
+ @?= Inside
+ classify IntelDoitm (x86 [ 0x48, 0x0f, 0x44, 0xc3 ] "cmove"
+ "rax, rbx") @?= Inside
+ classify IntelDoitm (x86 [ 0x48, 0xb8, 1, 0, 0, 0, 0, 0, 0, 0 ]
+ "movabs" "rax, 0x1") @?= Inside
+ classify IntelDoitm (x86 [ 0xc5, 0xf5, 0xd4, 0xc2 ] "vpaddq"
+ "ymm0, ymm1, ymm2") @?= Inside
+ classify IntelDoitm (x86 [ 0x75, 0x02 ] "jne" "0x10") @?= Excluded
+ classify IntelDoitm (x86 [ 0x90 ] "nop" "") @?= Excluded
+
+ , testCase "x86_64: outside DOITM, with the registers read" $ do
+ -- popcnt only writes its destination
+ classify IntelDoitm (x86 [ 0xf3, 0x48, 0x0f, 0xb8, 0xc3 ] "popcnt"
+ "rax, rbx")
+ @?= Watched [ Register "rbx" 0 64 ] False
+ classify IntelDoitm (x86 [ 0x92 ] "xchg" "eax, edx")
+ @?= Watched [ Register "rax" 0 32, Register "rdx" 0 32 ] False
+ -- a legacy SSE division reads its destination too
+ classify IntelDoitm (x86 [ 0xf2, 0x0f, 0x5e, 0xc1 ] "divsd"
+ "xmm0, xmm1")
+ @?= Watched [ Register "xmm0" 0 128, Register "xmm1" 0 128 ] False
+ classify IntelDoitm (x86 [ 0x98 ] "cwde" "")
+ @?= Watched [ Register "rax" 0 16 ] False
+ -- a memory operand's registers are its address's, not its data
+ classify IntelDoitm (x86 [ 0x0f, 0x54, 0x07 ] "andps"
+ "xmm0, xmmword ptr [rdi]")
+ @?= Watched [ Register "xmm0" 0 128 ] True
+
+ , testCase "llvm-objdump's lines are read" $ do
+ readDisassembly (T.unlines
+ [ "0000000000001000 <f>:"
+ , " 1000: 48 89 e5 \tmov\trbp, rsp"
+ , " 1003: f3 48 ab \trep\t\tstosq\tqword \
+ \ptr es:[rdi], rax"
+ , " 1006: 48 8b 05 4d b5 06 00 \tmov\trax, qword ptr \
+ \[rip + 0x6b54d] # 0x86d58 <x>"
+ , "\t\t..."
+ , " 1b824: 9112a000 \tadd\tx0, x0, #0x4a8" ])
+ @?= [ Line 0x1000 [ 0x48, 0x89, 0xe5 ] [] "mov" "rbp, rsp"
+ , Line 0x1003 [ 0xf3, 0x48, 0xab ] [ "rep" ] "stosq"
+ "qword ptr es:[rdi], rax"
+ , Line 0x1006 [ 0x48, 0x8b, 0x05, 0x4d, 0xb5, 0x06, 0x00 ] []
+ "mov" "rax, qword ptr [rip + 0x6b54d]"
+ , Line 0x1b824 [ 0x9112a000 ] [] "add" "x0, x0, #0x4a8" ]
+
+ , testCase "the watch list names what lies outside" $
+ watchSection IntelDoitm "/lib.so"
+ [ x86 [ 0x48, 0xf7, 0xf6 ] "div" "rsi"
+ , x86 [ 0x48, 0x01, 0xd8 ] "add" "rax, rbx"
+ , x86 [ 0x92 ] "xchg" "eax, edx" ]
+ @?= T.unlines
+ [ "O /lib.so", "D 0 div rsi"
+ , "U 0 0 2 rax:0:32 rdx:0:32 xchg eax, edx" ]
+ ]
+ where
+ word w = Line 0 [ w ] [] "" ""
+ x86 bs m ops = Line 0 bs [] m ops
+
diffTests :: TestTree
diffTests = testGroup "diff"
[ testCase "a dump reads whole" $ do
@@ -299,6 +389,36 @@ diffTests = testGroup "diff"
-- a control dividing other operands sets it apart as unsteady
fmap inPc (dvUnsteady (diffControlled [ x ] [ a, b ])) @?= [ 0x40 ]
+ , testCase "an instruction outside the contract is reported apart" $ do
+ -- 0x40 runs once in every run, outside the contract, on other
+ -- operands in B; 0x30 is watched too, on the same operands
+ let under d = d <> "U 30 7777\nW 30 popcnt rax, rbx\nU 40 "
+ a <- either assertFailure pure
+ (readDump (under dumpA <> "1111\nM x86_64\nG intel-doitm\n"))
+ b <- either assertFailure pure
+ (readDump (under dumpB <> "2222\nM x86_64\nG intel-doitm\n"))
+ x <- either assertFailure pure
+ (readDump (under dumpA <> "3333\nM x86_64\nG intel-doitm\n"))
+ dpIsa a @?= Just "x86_64"
+ dpContract a @?= Just "intel-doitm"
+ M.lookup 0x30 (dpTexts a) @?= Just "popcnt rax, rbx"
+ let dv = diffDumps [ a, b ]
+ -- not an origin: the contract says nothing either way of it
+ fmap (\(o, i) -> (o, inPc i)) (dvOrigins dv)
+ @?= [ (ControlOrigin, 0x10), (AddressOrigin, 0x20) ]
+ fmap inPc (dvOutside dv) @?= [ 0x40 ]
+ M.lookup 0x40 (dvOutsideBehaviour (diffDumps [ a, b, a ]))
+ @?= Just ([ [ 0, 2 ], [ 1 ] ], [])
+ dvWatched dv @?= M.fromList [ ("/lib.so", S.fromList [ 0x30, 0x40 ]) ]
+ notElem 0x40 (fmap inPc (dvDownstream dv)) @? "downstream"
+ -- runs alike in their operands show nothing outside
+ dvOutside (diffDumps [ a, a ]) @?= []
+ -- a control on other operands sets it apart as unsteady
+ dvOutside (diffControlled [ x ] [ a, b ]) @?= []
+ fmap inPc (dvUnsteady (diffControlled [ x ] [ a, b ])) @?= [ 0x40 ]
+ -- and the objects kept are the objects reported
+ dvOutside (restrictTo [ "/other.so" ] dv) @?= []
+
, testCase "an origin is given the calls that reached it" $ do
-- 0x10 ran in context 2 (the call at 0x40 made in context 1,
-- the call at 0x30 made in the program's own) in A, and in the
diff --git a/vestigia.cabal b/vestigia.cabal
@@ -29,7 +29,11 @@ library
c-sources:
cbits/norandom.c
exposed-modules:
- Vestigia.Diff
+ Vestigia.Contract
+ , Vestigia.Contract.Arm
+ , Vestigia.Contract.Intel
+ , Vestigia.Contract.Types
+ , Vestigia.Diff
, Vestigia.Json
, Vestigia.Layout
, Vestigia.Memcheck
